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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip MIPI DPHY with additional LVDS/TTL modes
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
"#phy-cells":
const: 0
"#clock-cells":
const: 0
compatible:
enum:
- rockchip,px30-dsi-dphy
- rockchip,rk3128-dsi-dphy
- rockchip,rk3368-dsi-dphy
reg:
maxItems: 1
clocks:
items:
- description: PLL reference clock
- description: Module clock
clock-names:
items:
- const: ref
- const: pclk
power-domains:
maxItems: 1
description: phandle to the associated power domain
resets:
items:
- description: exclusive PHY reset line
reset-names:
items:
- const: apb
required:
- "#phy-cells"
- "#clock-cells"
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
additionalProperties: false
examples:
- |
dsi_dphy: phy@ff2e0000 {
compatible = "rockchip,px30-video-phy";
reg = <0x0 0xff2e0000 0x0 0x10000>;
clocks = <&pmucru 13>, <&cru 12>;
clock-names = "ref", "pclk";
#clock-cells = <0>;
resets = <&cru 12>;
reset-names = "apb";
#phy-cells = <0>;
};
...
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