blob: 5f8b85d2b4b1b0eecd086afea9d9a8d28a9fd270 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_MME_CMDQ_REGS_H_
#define ASIC_REG_MME_CMDQ_REGS_H_
/*
*****************************************
* MME_CMDQ (Prototype: CMDQ)
*****************************************
*/
#define mmMME_CMDQ_GLBL_CFG0 0xD9000
#define mmMME_CMDQ_GLBL_CFG1 0xD9004
#define mmMME_CMDQ_GLBL_PROT 0xD9008
#define mmMME_CMDQ_GLBL_ERR_CFG 0xD900C
#define mmMME_CMDQ_GLBL_ERR_ADDR_LO 0xD9010
#define mmMME_CMDQ_GLBL_ERR_ADDR_HI 0xD9014
#define mmMME_CMDQ_GLBL_ERR_WDATA 0xD9018
#define mmMME_CMDQ_GLBL_SECURE_PROPS 0xD901C
#define mmMME_CMDQ_GLBL_NON_SECURE_PROPS 0xD9020
#define mmMME_CMDQ_GLBL_STS0 0xD9024
#define mmMME_CMDQ_GLBL_STS1 0xD9028
#define mmMME_CMDQ_CQ_CFG0 0xD90B0
#define mmMME_CMDQ_CQ_CFG1 0xD90B4
#define mmMME_CMDQ_CQ_ARUSER 0xD90B8
#define mmMME_CMDQ_CQ_PTR_LO 0xD90C0
#define mmMME_CMDQ_CQ_PTR_HI 0xD90C4
#define mmMME_CMDQ_CQ_TSIZE 0xD90C8
#define mmMME_CMDQ_CQ_CTL 0xD90CC
#define mmMME_CMDQ_CQ_PTR_LO_STS 0xD90D4
#define mmMME_CMDQ_CQ_PTR_HI_STS 0xD90D8
#define mmMME_CMDQ_CQ_TSIZE_STS 0xD90DC
#define mmMME_CMDQ_CQ_CTL_STS 0xD90E0
#define mmMME_CMDQ_CQ_STS0 0xD90E4
#define mmMME_CMDQ_CQ_STS1 0xD90E8
#define mmMME_CMDQ_CQ_RD_RATE_LIM_EN 0xD90F0
#define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xD90F4
#define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT 0xD90F8
#define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT 0xD90FC
#define mmMME_CMDQ_CQ_IFIFO_CNT 0xD9108
#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO 0xD9120
#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI 0xD9124
#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO 0xD9128
#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI 0xD912C
#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO 0xD9130
#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI 0xD9134
#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO 0xD9138
#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI 0xD913C
#define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET 0xD9140
#define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xD9144
#define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xD9148
#define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xD914C
#define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xD9150
#define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET 0xD9154
#define mmMME_CMDQ_CP_FENCE0_RDATA 0xD9158
#define mmMME_CMDQ_CP_FENCE1_RDATA 0xD915C
#define mmMME_CMDQ_CP_FENCE2_RDATA 0xD9160
#define mmMME_CMDQ_CP_FENCE3_RDATA 0xD9164
#define mmMME_CMDQ_CP_FENCE0_CNT 0xD9168
#define mmMME_CMDQ_CP_FENCE1_CNT 0xD916C
#define mmMME_CMDQ_CP_FENCE2_CNT 0xD9170
#define mmMME_CMDQ_CP_FENCE3_CNT 0xD9174
#define mmMME_CMDQ_CP_STS 0xD9178
#define mmMME_CMDQ_CP_CURRENT_INST_LO 0xD917C
#define mmMME_CMDQ_CP_CURRENT_INST_HI 0xD9180
#define mmMME_CMDQ_CP_BARRIER_CFG 0xD9184
#define mmMME_CMDQ_CP_DBG_0 0xD9188
#define mmMME_CMDQ_CQ_BUF_ADDR 0xD9308
#define mmMME_CMDQ_CQ_BUF_RDATA 0xD930C
#endif /* ASIC_REG_MME_CMDQ_REGS_H_ */
|
