blob: c3e69062b135aa66193efeabdfb1e5bfd3dc0bef (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
|
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_MMU_MASKS_H_
#define ASIC_REG_MMU_MASKS_H_
/*
*****************************************
* MMU (Prototype: MMU)
*****************************************
*/
/* MMU_INPUT_FIFO_THRESHOLD */
#define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
#define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
#define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 4
#define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
#define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 8
#define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
#define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 12
#define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
#define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 16
#define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
#define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 20
#define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
#define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 24
#define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
/* MMU_MMU_ENABLE */
#define MMU_MMU_ENABLE_R_SHIFT 0
#define MMU_MMU_ENABLE_R_MASK 0x1
/* MMU_FORCE_ORDERING */
#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0
#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1
#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 1
#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2
#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 2
#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4
#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 3
#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8
#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 4
#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10
#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 5
#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20
#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 6
#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40
#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 8
#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100
#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 9
#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200
#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 10
#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400
#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 11
#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800
#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 12
#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000
#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 13
#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000
#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 14
#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000
/* MMU_FEATURE_ENABLE */
#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1
#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2
#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3
#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4
#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10
#define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5
#define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20
/* MMU_VA_ORDERING_MASK_31_7 */
#define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0
#define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF
/* MMU_VA_ORDERING_MASK_49_32 */
#define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0
#define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF
/* MMU_LOG2_DDR_SIZE */
#define MMU_LOG2_DDR_SIZE_R_SHIFT 0
#define MMU_LOG2_DDR_SIZE_R_MASK 0xFF
/* MMU_SCRAMBLER */
#define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0
#define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F
#define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6
#define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40
#define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7
#define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80
/* MMU_MEM_INIT_BUSY */
#define MMU_MEM_INIT_BUSY_DATA_SHIFT 0
#define MMU_MEM_INIT_BUSY_DATA_MASK 0x3
#define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2
#define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4
#define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3
#define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8
/* MMU_SPI_MASK */
#define MMU_SPI_MASK_R_SHIFT 0
#define MMU_SPI_MASK_R_MASK 0xFF
/* MMU_SPI_CAUSE */
#define MMU_SPI_CAUSE_R_SHIFT 0
#define MMU_SPI_CAUSE_R_MASK 0xFF
/* MMU_PAGE_ERROR_CAPTURE */
#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0
#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18
#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
/* MMU_PAGE_ERROR_CAPTURE_VA */
#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
/* MMU_ACCESS_ERROR_CAPTURE */
#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0
#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18
#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
/* MMU_ACCESS_ERROR_CAPTURE_VA */
#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
#endif /* ASIC_REG_MMU_MASKS_H_ */
|
