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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_
#define ASIC_REG_PSOC_MME_PLL_REGS_H_
/*
*****************************************
* PSOC_MME_PLL (Prototype: PLL)
*****************************************
*/
#define mmPSOC_MME_PLL_NR 0xC71100
#define mmPSOC_MME_PLL_NF 0xC71104
#define mmPSOC_MME_PLL_OD 0xC71108
#define mmPSOC_MME_PLL_NB 0xC7110C
#define mmPSOC_MME_PLL_CFG 0xC71110
#define mmPSOC_MME_PLL_LOSE_MASK 0xC71120
#define mmPSOC_MME_PLL_LOCK_INTR 0xC71128
#define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C
#define mmPSOC_MME_PLL_DATA_CHNG 0xC71130
#define mmPSOC_MME_PLL_RST 0xC71134
#define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150
#define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200
#define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204
#define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208
#define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C
#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220
#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224
#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228
#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C
#define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280
#define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284
#define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288
#define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C
#define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0
#define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4
#define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8
#define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC
#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0
#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4
#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8
#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC
#define mmPSOC_MME_PLL_CLK_GATER 0xC71300
#define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310
#define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314
#define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318
#define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C
#define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400
#define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410
#define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420
#define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430
#define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440
#endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */
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