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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
 */

#include <asm/fpu/api.h>
#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/intel-family.h>

asmlinkage void chacha_block_xor_ssse3(u32 *state, u8 *dst, const u8 *src,
				       unsigned int len, int nrounds);
asmlinkage void chacha_4block_xor_ssse3(u32 *state, u8 *dst, const u8 *src,
					unsigned int len, int nrounds);
asmlinkage void hchacha_block_ssse3(const u32 *state, u32 *out, int nrounds);
asmlinkage void chacha_2block_xor_avx2(u32 *state, u8 *dst, const u8 *src,
				       unsigned int len, int nrounds);
asmlinkage void chacha_4block_xor_avx2(u32 *state, u8 *dst, const u8 *src,
				       unsigned int len, int nrounds);
asmlinkage void chacha_8block_xor_avx2(u32 *state, u8 *dst, const u8 *src,
				       unsigned int len, int nrounds);
asmlinkage void chacha_2block_xor_avx512vl(u32 *state, u8 *dst, const u8 *src,
					   unsigned int len, int nrounds);
asmlinkage void chacha_4block_xor_avx512vl(u32 *state, u8 *dst, const u8 *src,
					   unsigned int len, int nrounds);
asmlinkage void chacha_8block_xor_avx512vl(u32 *state, u8 *dst, const u8 *src,
					   unsigned int len, int nrounds);

static bool chacha20_use_ssse3 __ro_after_init;
static bool chacha20_use_avx2 __ro_after_init;
static bool chacha20_use_avx512vl __ro_after_init;
static bool *const chacha20_nobs[] __initconst = {
	&chacha20_use_ssse3, &chacha20_use_avx2, &chacha20_use_avx512vl };

static void __init chacha20_fpu_init(void)
{
	chacha20_use_ssse3 = boot_cpu_has(X86_FEATURE_SSSE3);
	chacha20_use_avx2 =
		boot_cpu_has(X86_FEATURE_AVX) &&
		boot_cpu_has(X86_FEATURE_AVX2) &&
		cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
	chacha20_use_avx512vl =
		boot_cpu_has(X86_FEATURE_AVX) &&
		boot_cpu_has(X86_FEATURE_AVX2) &&
		boot_cpu_has(X86_FEATURE_AVX512F) &&
		boot_cpu_has(X86_FEATURE_AVX512VL) &&
		boot_cpu_has(X86_FEATURE_AVX512BW) &&
		cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM |
				  XFEATURE_MASK_AVX512, NULL);
}

static void chacha20_avx512vl(struct chacha20_ctx *ctx, u8 *dst,
			      const u8 *src, unsigned int bytes)
{
	while (bytes >= CHACHA20_BLOCK_SIZE * 8) {
		chacha_8block_xor_avx512vl(ctx->state, dst, src, bytes, 20);
		bytes -= CHACHA20_BLOCK_SIZE * 8;
		src += CHACHA20_BLOCK_SIZE * 8;
		dst += CHACHA20_BLOCK_SIZE * 8;
		ctx->counter[0] += 8;
	}
	if (bytes > CHACHA20_BLOCK_SIZE * 4)
		chacha_8block_xor_avx512vl(ctx->state, dst, src, bytes, 20);
	else if (bytes > CHACHA20_BLOCK_SIZE * 2)
		chacha_4block_xor_avx512vl(ctx->state, dst, src, bytes, 20);
	else if (bytes)
		chacha_2block_xor_avx512vl(ctx->state, dst, src, bytes, 20);
	ctx->counter[0] += round_up(bytes, CHACHA20_BLOCK_SIZE);
}

static void chacha20_avx2(struct chacha20_ctx *ctx, u8 *dst,
			  const u8 *src, unsigned int bytes)
{
	while (bytes >= CHACHA20_BLOCK_SIZE * 8) {
		chacha_8block_xor_avx2(ctx->state, dst, src, bytes, 20);
		bytes -= CHACHA20_BLOCK_SIZE * 8;
		src += CHACHA20_BLOCK_SIZE * 8;
		dst += CHACHA20_BLOCK_SIZE * 8;
		ctx->counter[0] += 8;
	}
	if (bytes > CHACHA20_BLOCK_SIZE * 4)
		chacha_8block_xor_avx2(ctx->state, dst, src, bytes, 20);
	else if (bytes > CHACHA20_BLOCK_SIZE * 2)
		chacha_4block_xor_avx2(ctx->state, dst, src, bytes, 20);
	else if (bytes)
		chacha_2block_xor_avx2(ctx->state, dst, src, bytes, 20);
	ctx->counter[0] += round_up(bytes, CHACHA20_BLOCK_SIZE);
}

static void chacha20_ssse3(struct chacha20_ctx *ctx, u8 *dst,
			   const u8 *src, unsigned int bytes)
{
	while (bytes >= CHACHA20_BLOCK_SIZE * 4) {
		chacha_4block_xor_ssse3(ctx->state, dst, src, bytes, 20);
		bytes -= CHACHA20_BLOCK_SIZE * 4;
		src += CHACHA20_BLOCK_SIZE * 4;
		dst += CHACHA20_BLOCK_SIZE * 4;
		ctx->counter[0] += 4;
	}
	if (bytes > CHACHA20_BLOCK_SIZE)
		chacha_4block_xor_ssse3(ctx->state, dst, src, bytes, 20);
	else if (bytes)
		chacha_block_xor_ssse3(ctx->state, dst, src, bytes, 20);
	ctx->counter[0] += round_up(bytes, CHACHA20_BLOCK_SIZE);
}

static inline bool chacha20_arch(struct chacha20_ctx *ctx, u8 *dst,
				 const u8 *src, size_t len,
				 simd_context_t *simd_context)
{
	/* SIMD disables preemption, so relax after processing each page. */
	BUILD_BUG_ON(PAGE_SIZE < CHACHA20_BLOCK_SIZE ||
		     PAGE_SIZE % CHACHA20_BLOCK_SIZE);

	if (!IS_ENABLED(CONFIG_AS_SSSE3) || !chacha20_use_ssse3 ||
	    len <= CHACHA20_BLOCK_SIZE || !simd_use(simd_context))
		return false;

	for (;;) {
		const size_t bytes = min_t(size_t, len, PAGE_SIZE);

		if (IS_ENABLED(CONFIG_AS_AVX512) && chacha20_use_avx512vl)
			chacha20_avx512vl(ctx, dst, src, bytes);
		else if (IS_ENABLED(CONFIG_AS_AVX2) && chacha20_use_avx2)
			chacha20_avx2(ctx, dst, src, bytes);
		else
			chacha20_ssse3(ctx, dst, src, bytes);
		len -= bytes;
		if (!len)
			break;
		dst += bytes;
		src += bytes;
		simd_relax(simd_context);
	}

	return true;
}

static inline bool hchacha20_arch(u32 derived_key[CHACHA20_KEY_WORDS],
				  const u8 nonce[HCHACHA20_NONCE_SIZE],
				  const u8 key[HCHACHA20_KEY_SIZE],
				  simd_context_t *simd_context)
{
	if (IS_ENABLED(CONFIG_AS_SSSE3) && chacha20_use_ssse3 &&
	    simd_use(simd_context)) {
		u32 x[] __aligned(16) = {
			CHACHA20_CONSTANT_EXPA,
			CHACHA20_CONSTANT_ND_3,
			CHACHA20_CONSTANT_2_BY,
			CHACHA20_CONSTANT_TE_K,
			get_unaligned_le32(key +  0),
			get_unaligned_le32(key +  4),
			get_unaligned_le32(key +  8),
			get_unaligned_le32(key + 12),
			get_unaligned_le32(key + 16),
			get_unaligned_le32(key + 20),
			get_unaligned_le32(key + 24),
			get_unaligned_le32(key + 28),
			get_unaligned_le32(nonce +  0),
			get_unaligned_le32(nonce +  4),
			get_unaligned_le32(nonce +  8),
			get_unaligned_le32(nonce + 12)
		};

		hchacha_block_ssse3(x, derived_key, 20);
		return true;
	}
	return false;
}