linux-rng/drivers/gpu/drm/amd/display/amdgpu_dm, branch master

drm/amd/display: fix dc_lock leak on GPU reset error paths

2026-08-25T22:24:30Z

On GPU reset, dm_suspend() takes dc_lock and leaves it for dm_resume() to drop. If amdgpu_dm_commit_zero_streams() or dm_dmub_hw_init() fails, the function returns with the lock still held. The matching resume path is then skipped, so every later dc_lock take hangs. Release the cached DC state and unlock before returning the error. Fixes: 3cf7a0bc87f0 ("drm/amd/display: Catch failures for amdgpu_dm_commit_zero_streams()") Fixes: 2b6943df5413 ("drm/amd/display: Pass up errors for reset GPU that fails to init HW") Cc: stable@vger.kernel.org Signed-off-by: Linkai Gong Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amd/display: Log details when failing to register HPD IRQ

2026-08-25T22:21:24Z

This should help diagnose HPD IRQ related issues in the future. Signed-off-by: Timur Kristóf Reviewed-by: Mario Limonciello (AMD) Link: https://patch.msgid.link/20260821215059.312868-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amd/display: validate plane degamma LUT size for private color prop

2026-08-19T14:14:55Z

Unlike the CRTC degamma path, which is guarded by amdgpu_dm_verify_lut_sizes(), the per-plane degamma LUT size was never validated before use. __set_dm_plane_degamma() passed the user-supplied size straight into __is_lut_linear() and, for a non-linear LUT, into __set_input_tf() -> __drm_lut_to_dc_gamma(), the latter always iterating MAX_COLOR_LUT_ENTRIES entries regardless of the actual LUT size. A malformed AMD_PLANE_DEGAMMA_LUT blob (e.g. a single entry) could thus trigger a divide-by-zero in __is_lut_linear() or an out-of-bounds read in __drm_lut_to_dc_gamma(). Reject any plane degamma LUT whose size does not match MAX_COLOR_LUT_ENTRIES, mirroring the invariant the code already asserts a few lines below (and which the CRTC path enforces). The AMD_PLANE_DEGAMMA_LUT property is only exposed on builds with AMD_PRIVATE_COLOR defined. Fixes: 980f8710075a ("drm/amd/display: add plane degamma TF and LUT support") Cc: stable@vger.kernel.org Signed-off-by: Harry Wentland Reviewed-by: Melissa Wen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: avoid divide-by-zero in __is_lut_linear()

2026-08-19T14:14:28Z

__is_lut_linear() computes the expected value of each entry with expected = i * MAX_DRM_LUT_VALUE / (size - 1); If it is ever called with a single-entry LUT, size - 1 is zero and the kernel takes a divide error (#DE). A LUT with fewer than two entries cannot describe a linear mapping anyway, so return false early instead of dividing by zero. Fixes: 086247a4b2fb ("drm/amd/display: Use 4096 lut entries") Cc: stable@vger.kernel.org Signed-off-by: Harry Wentland Reviewed-by: Melissa Wen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Scale custom brightness curve from full range

2026-08-19T14:03:37Z

Custom brightness curves use an 8-bit input signal. After exporting the full PWM range to userspace, the curve normalizer still divides requests by the physical PWM span. On panels with a nonzero minimum PWM level, this can produce a curve input greater than 255 and send an invalid backlight level to DC. Scale the userspace [0..max] range to the curve's [0..255] range instead. This retains the full advertised range and keeps the reverse readback conversion unchanged. Fixes: 8dbd72cb7900 ("drm/amd/display: Export full brightness range to userspace") Cc: stable@vger.kernel.org Signed-off-by: Akhmed Zhitaev Reviewed-by: Mario Limonciello (AMD) (Move to amdgpu_dm_backlight.c) Link: https://patch.msgid.link/20260813170959.22073-1-zhitaevakh@gmail.com Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amd/display: make DC_RUN_WITH_PREEMPTION_ENABLED misuse a build error

2026-08-12T13:45:03Z

Inside an FPU compilation unit DC_FP_START() and DC_FP_END() are defined as BUILD_BUG(), so using them there fails the build. That was done on purpose by commit a574f53ed52e ("drm/amd/display: Permit DC_FP_START/END only in non-FP compilation units"). DC_RUN_WITH_PREEMPTION_ENABLED() was added later by commit 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1") and defined as a plain pass-through in that same branch instead. A wrap placed inside an FPU compilation unit therefore compiles cleanly, reads as correct during review, and does nothing at all. This is not hypothetical. While chasing a "scheduling while atomic" splat in dc_create_plane_state() on PREEMPT_RT, an attempt to place the guard further up the call chain, in dml21_add_phantom_plane() in dc/dml2_0/dml21/dml21_utils.c, had no effect for exactly this reason: dc/dml2_0/Makefile applies CC_FLAGS_FPU to every object under that directory, and the top level Makefile adds -D_LINUX_FPU_COMPILATION_UNIT to CC_FLAGS_FPU. Define the macro as BUILD_BUG() there as well, so that the mistake is a compile error rather than a guard that silently does nothing. The code argument is kept in the expansion so the BUILD_BUG() failure is not accompanied by set-but-unused diagnostics for variables assigned inside it. No current user is affected. dc/core/dc_stream.c and dc/resource/dcn32/dcn32_resource.c are outside the dml directories, and dc/dml2_0/dml2_wrapper.c and dc/dml2_0/dml21/dml21_wrapper.c are built without the FPU flags because dc/dml2_0/Makefile replaces their CFLAGS with CC_FLAGS_NO_FPU and removes CC_FLAGS_FPU. Link: https://lore.kernel.org/all/1ead313022bc62dce1f42af9f855727eb9074443.camel@web.de/ Signed-off-by: Mikhail Gavrilov Reviewed-by: Tom Chung Signed-off-by: Alex Deucher

drm/amd/display: Fix NULL pointer dereference in amdgpu_dm_crtc_set_vblank()

2026-08-12T13:38:11Z

amdgpu_dm_crtc_set_vblank() dereferences acrtc_state->stream when vblank is enabled/queried from DRM_IOCTL_MODE_CRTC_GET_SEQUENCE before a stream is attached to it. BUG: kernel NULL pointer dereference, address: 0000000000000008 RIP: amdgpu_dm_crtc_set_vblank+0x6b/0x4d0 [amdgpu] Call Trace: drm_vblank_enable drm_vblank_get drm_crtc_get_sequence_ioctl drm_ioctl_kernel drm_ioctl Reproduced by running VKCTS with WSI tests enabled on RADV. Guard the enable path on acrtc_state->stream being non-NULL, matching the existing checks in this function. Fixes: 34d66bc7ff10 ("drm/amd/display: Fix Xorg desktop unresponsive on Replay panel") Reviewed-by: Melissa Wen Signed-off-by: Samuel Pitoiset Signed-off-by: Alex Deucher

drm/amd/display: Set native cursor mode for disabled CRTCs again

2026-08-06T17:45:44Z

It was regressed by a refactor. Let's fix it again. Always set native cursor mode when the CRTC is disabled, to make sure it doesn't cause atomic commits to fail when they are trying to disable the CRTC. Fixes: 87a6dab12fc0 ("drm/amd/display: add cursor module") Cc: Alex Hung Reviewed-by: Ivan Lipski Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher

drm/amd/display: allow self-refresh exit while entry is blocked

2026-08-06T16:48:00Z

amdgpu_dm_crtc_set_static_screen_optimze() maps sso_enable to the Replay and PSR1 vsync events. allow_sr_entry is an entry gate, but the helper currently applies it to both directions. A non-fast update clears allow_sr_entry. During a modeset, a separate hardware-programming event keeps self-refresh blocked while the stream is reprogrammed. If vblank is enabled before the entry delay expires, the ISM calls the helper with sso_enable false. The early return drops the disable request, so the vsync events are not set. After enough fast commits, allow_sr_entry becomes true and the hardware-programming event can be cleared. Since the vblank reference remains held, there is no further zero-to-one vblank transition to restore the missing vsync events. Replay or PSR1 can then become active while vblank is still enabled. Gate only requests that enable static-screen optimization. Always process disable requests so a vblank requestor keeps Replay and PSR1 blocked. On a Phoenix system, repeated SDDM-to-VT handoffs produced stuck flips followed by flip_done and commit-wait timeouts. The timeout was not observed with this change applied. Fixes: 3c108046e1d6 ("drm/amd/display: Add power module on Linux") Assisted-by: Codex:gpt-5.6-sol Assisted-by: Claude:opus-5 Signed-off-by: David Weber Reviewed-by: Leo Li Signed-off-by: Alex Deucher

drm/amd: Disable DP audio spread spectrum for Cyan Skillfish

2026-08-06T16:47:56Z

The VBIOS for Cyan Skillfish devices (DCN201) indicates there is DisplayPort ref clock spread spectrum downspread, so the audio clock is corrected for it. However, the clock source in this hardware does not seem to actually be running with a clock downspread, so DisplayPort audio desyncs with video after several minutes. Ignore dprefclk SS downspread on CYAN_SKILLFISH2 asic. Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5429 Signed-off-by: Travis K. Bangs Signed-off-by: Alex Deucher