linux-rng/drivers/gpu/drm/amd/display/dc/core, branch master

drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix

2026-08-12T13:42:44Z

COLOR_SPACE_YCBCR2020_TYPE, which is selected for COLOR_SPACE_2020_YCBCR_LIMITED color_space, has coefficients that are incorrect for limited-range output. Its luma and chroma scaling is full-range so output is too bright and colors are incorrect. COLOR_SPACE_YCBCR2020_TYPE is closer to a full-range conversion matrix with incorrect luma offset, so correct the luma offset for full-range and rename it to COLOR_SPACE_YCBCR2020_FULL_TYPE. Add COLOR_SPACE_YCBCR2020_LIMITED_TYPE with correct scaling and range for limited-range output. Fix related functions so COLOR_SPACE_YCBCR2020_LIMITED_TYPE and COLOR_SPACE_YCBCR2020_FULL_TYPE are correctly selected based on dc_color_space. Derivation of both matrices follows ITU-T H.273: Table 4, MatrixCoefficients 9, BT.2020-NCL weights: KR = 0.2627, KB = 0.0593, KG = 1 - KR - KB = 0.6780. Equations 45-47 in matrix form: [ KR KG KB 0 ] M2020_NCL = [ -KR/(2(1-KB)) -KG/(2(1-KB)) 1/2 0 ] [ 1/2 -KG/(2(1-KR)) -KB/(2(1-KR)) 0 ] [ 0 0 0 1 ] Limited and Full transforms based on equations 30-32 and 36-38 with bit depth 10, normalized by 1023: [ 876/1023 0 0 64/1023 ] MLimited = [ 0 896/1023 0 512/1023 ] [ 0 0 896/1023 512/1023 ] [ 0 0 0 1 ] [ 1023/1023 0 0 0 ] MFull = [ 0 1023/1023 0 512/1023 ] [ 0 0 1023/1023 512/1023 ] [ 0 0 0 1 ] M2020_NCL_Limited = MLimited x M2020_NCL M2020_NCL_Full = MFull x M2020_NCL The upper three rows of M2020_NCL_* are stored in CR, Y, CB order. Each M2020_NCL_* value is stored as Round(value * 8192) in its 16-bit two's-complement representation. Fixes: 973a9c810c78 ("drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix") Assisted-by: OpenAI-Codex:GPT-5.6-Sol Tested-by: Igor Paunovic Tested-by: Satyajit Roy Signed-off-by: Nathan Lucas Signed-off-by: Alex Deucher

drm/amd/display: Fix crash in hwss_set_output_transfer_func()

2026-08-06T17:46:24Z

The pipe_ctx->plane_res.hubp pointer is NULL on all DCE hardware, which causes a kernel NULL pointer dereference on all Vega and older GPUs. Let's add a simple NULL check. Fixes: 6bfca938471b ("drm/amd/display: Refactor DPP_SET_OUTPUT_TRANSFER_FUNC to drop pipe_ctx") Signed-off-by: Timur Kristóf Cc: Tomasz Siemek Signed-off-by: Alex Deucher

drm/amd/display: Migrate color manager HW and fix MCM blend LUT issues

2026-08-06T16:44:26Z

Combine two related color manager improvements: 1. Migrate MCM/RMCM, shaper and 3DLUT HW programming to dc_plane_cm - Continue convergence with upstream Color Manager refactor - Migrate MCM/RMCM, shaper and 3DLUT programming for dcn401+ to dc_plane_cm - Unify MCM programming across both legacy and 3DLUT DMA paths - Add 3DLUT DMA broadcast support for multi-pipe planes 2. Reprogram MCM blend LUT on blend_enable falling edge - Fix issue where SDR desktop remained desaturated after video playback - Detect blend_enable falling edge (1->0) in surface update detection - Force MCM LUT reprogramming on blend state change Reviewed-by: Dillon Varone Signed-off-by: Rafal Ostrowski Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable DCN6 sources compilation

2026-08-06T13:53:32Z

- Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai Signed-off-by: Roman Li Reviewed-by: Ivan Lipski Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add get replay residency function

2026-07-28T23:17:31Z

[Why&How] Add dc interface to export link service function for getting Replay residency Reviewed-by: Robin Chen Signed-off-by: Huang, Leon Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Use current mpc pipe in set output transfer func

2026-07-28T23:17:30Z

[why] Only the top pipe had the output transfer function programmed. [how] Program the current pipe from the MPC chain during fast sequence build. Reviewed-by: Martin Leung Reviewed-by: Alvin Lee Signed-off-by: Tomasz Siemek Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix force FRL rate debug setting

2026-07-28T22:58:15Z

[Why & How] - force FRL rate debug bit was not correctly forcing requested FRL rate Reviewed-by: Chris Park Signed-off-by: Relja Vojvodic Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42

2026-07-28T22:37:42Z

[Why] DCN must not gate DF C-state locally via the DCHUBBUB ALLOW_SELF_REFRESH controls: forcing a local "disallow" during MM-stutter re-entry can wedge the fabric and hang boot. When DCN is disallowing c-state or has invalid watermarks we should be explicit about it rather than using the watermark force selector. [How] Register DCN as a client of PMFW's DF C-state arbiter and signal over DALSMC whether DCN permits DF C-state; PMFW allows DF C-state only once every client (including DCN) has voted "allow". - dc_clocks.cstate_allow: last DCN vote acked by PMFW - clk_mgr_funcs::notify_cstate_disable(clk_mgr, disable) prepare_bandwidth and headless dc_power_down_on_boot vote Allow; hardware_release votes Disallow; init_clocks (D0 entry) only clears the cache (cstate_allow) so the next allow re-syncs with PMFW. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Make dc_state_update const in commit path

2026-07-28T22:37:36Z

[Why] The state-update commit path only reads the caller's update descriptor, it never mutates the dc_state_update root. Making the pointer const documents that contract. [How] Add const to the updates parameter of dc_update_state and dc_check_state_update. Mark the single-assignment locals in dc_update_state_init const and replace the memset plus field-by-field assignment with a compound literal initializer. Reviewed-by: Dominik Kaszewski Signed-off-by: Wenjing Liu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Wire probe commit path into dc_update_state

2026-07-28T22:37:33Z

[Why] The dc_update_state commit interface and the dc_probe object model existed but were not connected: there was no path to validate, commit, and program a probe through the update pipeline, nor to read the result back. The measurement waits on OTG frame edges and must not block fast updates. [How] - Move the per-commit scratch off dc_stream_state onto a dc-owned pool; acquire at init, release on cleanup or prepare failure, serialized by the DM global lock every commit path already holds. - dc_update_state drives stream commits, probe-only commits, or both through one staged init/prepare/execute/cleanup loop with a null-arg guard. prepare releases the scratch slot on failure; cleanup releases it on success. - Probe prepare installs the absolute probe set in place; execute calls the perfmon programming hook in the unlocked window and latches results. - Add resource_validate_probe_set, a context-free achievability check shared by dc_validate_global_state (full update) and probe prepare (probe-only). - dc_state_get_status gains a probe status class with a probe filter and a by-type mapping; dc_validation_set gains probes/probe_count. Drop the dead actual_* fields from struct dc_qos_info. Reviewed-by: Dominik Kaszewski Signed-off-by: Wenjing Liu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher