Development tree for the kernel CSPRNG https://git.zx2c4.com/linux-rng/atom/tools?h=linus%2Fmaster 2025-06-08T18:44:41Z 2025-06-08T18:44:41Z Linus Torvalds torvalds@linux-foundation.org 2025-06-08T18:44:41Z urn:sha1:939f15e640f193616691d3bcde0089760e75b0d3 Pull turbostat updates from Len Brown: - Add initial DMR support, which required smarter RAPL probe - Fix AMD MSR RAPL energy reporting - Add RAPL power limit configuration output - Minor fixes * tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: tools/power turbostat: version 2025.06.08 tools/power turbostat: Add initial support for BartlettLake tools/power turbostat: Add initial support for DMR tools/power turbostat: Dump RAPL sysfs info tools/power turbostat: Avoid probing the same perf counters tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared tools/power turbostat: Clean up add perf/msr counter logic tools/power turbostat: Introduce add_msr_counter() tools/power turbostat: Remove add_msr_perf_counter_() tools/power turbostat: Remove add_cstate_perf_counter_() tools/power turbostat: Remove add_rapl_perf_counter_() tools/power turbostat: Quit early for unsupported RAPL counters tools/power turbostat: Always check rapl_joules flag tools/power turbostat: Fix AMD package-energy reporting tools/power turbostat: Fix RAPL_GFX_ALL typo tools/power turbostat: Add Android support for MSR device handling tools/power turbostat.8: pm_domain wording fix tools/power turbostat.8: fix typo: idle_pct should be pct_idle 2025-06-08T18:10:17Z Len Brown len.brown@intel.com 2025-06-08T16:31:59Z urn:sha1:42fd37dcc432df1ea1987232d41bb84fcb7e150c Add initial DMR support, which required smarter RAPL probe Fix AMD MSR RAPL energy reporting Add RAPL power limit configuration output Minor fixes Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:17Z Zhang Rui rui.zhang@intel.com 2025-04-18T06:04:26Z urn:sha1:d8c0f5d973004f2ac86375ea54fae9625ac594fb Add initial support for BartlettLake. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2024-03-04T06:54:40Z urn:sha1:83075bd59de25f5c9238a583008540914946f23e Add initial support for DMR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-30T06:01:31Z urn:sha1:2a535d6cc3b4831cc6dc7e248f2fb4afeeec591d for example: intel-rapl:1: psys 28.0s:100W 976.0us:100W intel-rapl:0: package-0 28.0s:57W,max:15W 2.4ms:57W intel-rapl:0/intel-rapl:0:0: core disabled intel-rapl:0/intel-rapl:0:1: uncore disabled intel-rapl-mmio:0: package-0 28.0s:28W,max:15W 2.4ms:57W [lenb: simplified format] Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> squish me Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-30T00:09:28Z urn:sha1:69078520fdf1525212a23a80dc79e1a75f2062f6 For the RAPL package energy status counter, Intel and AMD share the same perf_subsys and perf_name, but with different MSR addresses. Both rapl_counter_arch_infos[0] and rapl_counter_arch_infos[1] are introduced to describe this counter for different Vendors. As a result, the perf counter is probed twice, and causes a failure in in get_rapl_counters() because expected_read_size and actual_read_size don't match. Fix the problem by skipping the already probed counter. Note, this is not a perfect fix. For example, if different vendors/platforms use the same MSR value for different purpose, the code can be fooled when it probes a rapl_counter_arch_infos[] entry that does not belong to the running Vendor/Platform. In a long run, better to put rapl_counter_arch_infos[] into the platform_features so that this becomes Vendor/Platform specific. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-17T09:44:50Z urn:sha1:ff3d019e98db83ce2b5eb395333bc2518b37f4f0 platform_features->rapl_msrs describes the RAPL MSRs supported. While RAPL Perf counters can be exposed from different kernel backend drivers, e.g. RAPL MSR I/F driver, or RAPL TPMI I/F driver. Thus, turbostat should first blindly probe all the available RAPL Perf counters, and falls back to the RAPL MSR counters if they are listed in platform_features->rapl_msrs. With this, platforms that don't have RAPL MSRs can clear the platform_features->rapl_msrs bits and use RAPL Perf counters only. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-17T09:35:17Z urn:sha1:0362337968ad252e6563fff131906a43450d8940 Increase the code readability by moving the no_perf/no_msr flag and the cai->perf_name/cai->msr sanity checks into the counter probe functions. No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-17T07:58:51Z urn:sha1:1ab2e19b4c52ee08700938d52024d85bd15c9721 probe_rapl_msr() is reused for probing RAPL MSR counters, cstate MSR counters and MPERF/APERF/SMI MSR counters, thus its name is misleading. Similar to add_perf_counter(), introduce add_msr_counter() to probe a counter via MSR. Introduce wrapper function add_rapl_msr_counter() at the same time to add extra check for Zero return value for specified RAPL counters. No functional change intended. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-06-08T18:10:16Z Zhang Rui rui.zhang@intel.com 2025-05-17T09:40:08Z urn:sha1:3403e89f97ce71e473a5128ea389cb83bc27e7a9 As the only caller of add_msr_perf_counter_(), add_msr_perf_counter() just gives extra debug output on top. There is no need to keep both functions. Remove add_msr_perf_counter_() and move all the logic to add_msr_perf_counter(). No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>