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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-03-09 21:14:02 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-08 10:16:09 +0200 |
| commit | b6f2c6bd4e9ea47afa2b66c0c64c296a1fbf4489 (patch) | |
| tree | e0d358850ecf18bb965bc035cac5ec22a92adbcf /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzv2h: Rename PLL field macros for consistency (diff) | |
| download | linux-rng-b6f2c6bd4e9ea47afa2b66c0c64c296a1fbf4489.tar.xz linux-rng-b6f2c6bd4e9ea47afa2b66c0c64c296a1fbf4489.zip | |
clk: renesas: r9a09g057: Add clock and reset entries for GE3D
Add PLLGPU along with the necessary clock and reset entries for GE3D.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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