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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-03-09 21:14:00 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-08 10:16:09 +0200 |
| commit | fea942bc15135e065b456421f7a163df036242c5 (patch) | |
| tree | 3fe42e37f9fcc7f3df301003699f77f3d4f47365 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk` (diff) | |
| download | linux-rng-fea942bc15135e065b456421f7a163df036242c5.tar.xz linux-rng-fea942bc15135e065b456421f7a163df036242c5.zip | |
clk: renesas: rzv2h: Add support for enabling PLLs
Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being
disabled by default in TF-A. Add support for enabling PLL clocks in the
RZ/V2H(P) CPG driver to manage this.
Introduce `is_enabled` and `enable` callbacks to handle PLL state
transitions. With the `enable` callback, PLLGPU will be turned ON only
when the GPU node is enabled; otherwise, it will remain off. Define new
macros for PLL standby and monitor registers to facilitate this process.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions