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Merge "Zynq SoC changes for 3.20" from Michal Simek:
arm: Xilinx Zynq SoC patches for v3.20
- Enable pincontrol
- Simplified SLCR initialization
- Setup default ARCH_NR_GPIO
* tag 'zynq-soc-for-3.20' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: Simplify SLCR initialization
ARM: zynq: PM: Fixed simple typo.
ARM: zynq: Setup default gpio number for Xilinx Zynq
ARM: zynq: Enable pinctrl
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "Samsung mach updates for v3.20" from Kukjin Kim:
- add exynos3250 Supsend to RAM support
- recognize MFC v8 devices for exynos5422/5800
- print CPU id/rev during kernel boot
* tag 'samsung-update' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add exynos3250 suspend-to-ram support
ARM: EXYNOS: Recognize Samsung MFC v8 devices
ARM: SAMSUNG: print CPU id on probe
Signed-off-by: Olof Johansson <olof@lixom.net>
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The digicolor interrupt controller driver now needs syscon.
Also, as per clocksource maintainer request, we now have a separate config
symbol, CONFIG_DIGICOLOR_TIMER, for the digicolor timer.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Based on
"mfd: syscon: Decouple syscon interface from platform devices"
(sha1: bdb0066df96e74a4002125467ebe459feff1ebef)
SLCR driver can use syscon/regmap drivers directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Use the USART peripheral as UART for low level debug. Only the UA0 port is
currently supported.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add initial support for the Conexant CX92755 SoC. The CX92755 is one of the
Digicolor series of SoCs, all sharing many of the same peripherals. The code
was tested on the CX92755 evaluation kit, AKA Equinox.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "omap changes to make dm816x usable" from Tony Lindgren:
Patches to add necessary SoC related clockdomain and interconnect
data to make dm816x boot with basic devices. This finally gets
dm816x into a usable shape for further work to happen after a few
years of stalled effort of making this SoC to work with the mainline
kernel.
As most of the devices are similar to the other omap variants, we
get at least serial, MMC, Ethernet, I2C, EDMA, pinctrl, SPI and GPMC
working for these SoCs with the related device tree changes.
* tag 'omap-for-v3.20/dm816x-data' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Add dm816x hwmod support
ARM: OMAP2+: Add clock domain support for dm816x
ARM: OMAP2+: Add board-generic.c entry for ti81xx
ARM: OMAP2+: Disable omap3 PM init for ti81xx
ARM: OMAP2+: Fix reboot for 81xx
ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init
ARM: OMAP2+: Fix ti81xx class type
ARM: OMAP2+: Fix ti81xx devtype
ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "Allwinner core changes for 3.20" from Maxime Ripard:
- Support for the A31s
- Adding support for cpufreq using cpufreq-dt
* tag 'sunxi-core-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Register cpufreq-dt for sun[45678]i
ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "at91: cleanup/soc for 3.20 #3 (bis) from Nicolas Ferre:
Third batch of cleanup/soc for 3.20:
- several fixes and adjustments following the last cleanup batch
- removal of some unused Kconfig options
- slight PM and pm_idle rework to ease future rework
- removal of unneeded mach/system_rev.h
* tag 'at91-cleanup3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
ARM: at91: remove unused mach/system_rev.h
ARM: at91: stop using HAVE_AT91_DBGUx
ARM: at91: fix ordering of SRAM and PM initialization
ARM: at91: sam9: set arm_pm_idle from sam9_dt_device_init
ARM: at91: fix sam9n12 and sam9x5 arm_pm_idle
ARM: at91: mark const init data with __initconst instead of __initdata
ARM: at91: fix PM initialization for newer SoCs
ARM: at91: fix Kconfig.debug by adding DEBUG_AT91_UART option
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add minimal hwmod support that works at least on dm8168. This
is based on the code in the earlier TI CDP tree, and an earlier
patch by Aida Mynzhasova <aida.mynzhasova@skitlab.ru>.
I've set up things to work pretty much the same way as for
am33xx. We are basically using cm33xx.c with a different set
of clocks and clockdomains.
This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches
published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init() was substituted by
new ti81xx_clockdomains_init() while early initialization of
TI81XX platform.
Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX
block instead inside the ifdef block for omap3 to avoid make
randconfig build errors.
This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches
published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
[tony@atomide.com: updated to apply, renamed to clockdomains81xx.c,
fixed to use am33xx_clkdm_operations, various fixes suggested by
Paul Walmsley]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The SOC_AT91SAM9263 is being removed, stop using it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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mach/system_rev.h is not used, remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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In order to remove SOC_SAM9xxx options, stop using HAVE_AT91_DBGUx.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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The PM initialization needs internal SRAM for allocating a gen_pool and
use it to store its PM code. So we need to have of_platform_populate() before
this code.
Suggested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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As all sam9 SoCs are setting arm_pm_idle to at91sam9_idle(), do it from
sam9_dt_device_init().
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: adapt patch to newer series]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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sam9n12 and sam9x5 don't set arm_pm_idle because of an oversight, fix that.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with
error: $variablename causes a section type conflict
because a section containing const variables is marked read only and so
cannot contain non-const variables.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: update the paths after having re-arranged the patches]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller
and have a different PMC status register layout than the at91sam9g45. Create
another at91_sam9x5_pm_init() function to match this compatibility.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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The DEBUG_AT91_UART Kconfig option was forgotten when moving the
AT91 debug-macro.S file. Add it and use it for the at91.S compilation.
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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merge "qcom SoC changes for v3.20-2" from Kumar Gala:
Qualcomm ARM Based SoC Updates for v3.20-2
* Various bug fixes and minor feature additions to scm code
* Added big-endian support to debug MSM uart
* Added big-endian support to ARCH_QCOM
* Cleaned up some Kconfig options associated with ARCH_QCOM
* Added Andy Gross as co-maintainer
* tag 'qcom-soc-for-3.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
MAINTAINERS: Add co-maintainer for ARM/Qualcomm Support
ARM: qcom: Drop unnecessary selects from ARCH_QCOM
ARM: qcom: Fix SCM interface for big-endian kernels
ARM: qcom: scm: Clarify boot interface
ARM: qcom: Add SCM warmboot flags for quad core targets.
ARM: qcom: scm: Add logging of actual return code from scm call
ARM: qcom: scm: Flush the command buffer only instead of the entire cache
ARM: qcom: scm: Get cacheline size from CTR
ARM: qcom: scm: Fix incorrect cache invalidation
ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN
ARM: debug: msm: Support big-endian CPUs
ARM: debug: Update MSM and QCOM DEBUG_LL help
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: tegra: Core code changes for v3.20" from Thierry Reding:
This contains a couple of preparatory patches for 64-bit support. A new
feature is implemented in the power-management controller which allows
it to switch off the SoC if it overheats.
* tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc: tegra: Add thermal reset (thermtrip) support to PMC
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
of: Add descriptions of thermtrip properties to Tegra PMC bindings
soc/tegra: pmc: Add Tegra132 support
soc/tegra: fuse: Add Tegra132 support
soc/tegra: fuse: Constify tegra_fuse_info structures
soc/tegra: Add Tegra132 support
clocksource: Build Tegra timer on 32-bit ARM only
soc/tegra: pmc: restrict compilation of suspend-related support to ARM
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: imx: soc changes for 3.20" from Shawn Guo:
The i.MX SoC changes for 3.20:
- Add .disable_unused function hook for shared gate clock to ensure
the clock tree use count matches the hardware state
- Add a deeper idle state for i.MX6SX cpuidle driver powering off the
ARM core
- One correction on i.MX6Q esai_ipg parent clock setting
- Add a missing iounmap call for imx6q_opp_check_speed_grading()
- Add missing clocks for VF610 UART4, UART5 and SNVS blocks
- Expand VF610 device tree compatible matching table to cover more
Vybrid family SoCs
- Expand i.MX clk-pllv3 a bit with the shift for frequency multiplier
to support Vybrid's USB PLL oddity
* tag 'imx-soc-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: clk-imx6q: refine esai_ipg's parent
ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()
ARM: imx: clk-vf610: Add clock for SNVS
ARM: imx: clk-vf610: Add clock for UART4 and UART5
ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sx
ARM: imx: support arm power off in cpuidle for i.mx6sx
ARM: imx: remove unnecessary setting for DSM
ARM: imx: correct the hardware clock gate setting for shared nodes
ARM: imx: pllv3: add shift for frequency multiplier
ARM vf610: add compatibilty strings of supported Vybrid SoC's
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: mediatek: soc changes for v3.20" from Matthias Brugger:
This adds config options for the different Mediatek SoC. We need this so that
the pinctrl driver does not bloat the kernel binary.
Apart we change the Kconfig description and add the config option for mt6592
low-level debug option.
* tag 'v3.20-next-soc1' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: Low-level-debug for mt6592
ARM: mediatek: Add config options for mediatek SoCs.
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "mvebu/soc #2" from Andrew Lunn:
Soc patches for mvebu for v3.20, part #2.
* tag 'mvebu-soc-3.20-2' of git://git.infradead.org/linux-mvebu:
bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window
bus: mvebu-mbus: fix support of MBus window 13 on Armada XP/375/38x
ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O coherency
bus: mvebu-mbus: use automatic I/O synchronization barriers
bus: mvebu-mbus: fix support of MBus window 13
ARM: mvebu: completely disable hardware I/O coherency
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: rockchip: soc updates for v3.20" from Heiko Stübner:
SoC parts of basic suspend support and removal of
Cortex-A9 reference from the machine name.
* tag 'v3.20-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: remove cpu-core name from machine name
ARM: rockchip: Add pmu-sram binding
ARM: rockchip: add suspend and resume for RK3288
Signed-off-by: Olof Johansson <olof@lixom.net>
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Added myself as a co-maintainer. Updated the files to include the
Qualcomm SoC directory. Added linux-soc mailing list.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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We don't need to force gpiolib on everyone given that it isn't
required to actually boot the device and the multiplatform
Kconfig already selects ARCH_WANT_OPTIONAL_GPIOLIB. CLKSRC_OF is
already selected by CONFIG_ARCH_MULTIPLATFORM too, so we can drop
that here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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The secure environment only runs in little-endian mode, so any
buffers shared with the secure environment should have their
contents converted to little-endian. We also mark such elements
with __le32 to allow sparse to catch such problems.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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The secure world only knows about 32-bit wide physical addresses
for the boot API. Clarify the kernel interface by explicitly
stating a u32 instead of phys_addr_t which could be 32 or 64 bits
depending on LPAE or not.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required.
The thermtrip event is triggered by the soctherm block, and all
soctherm sensors default to showing a temperature of zero Celsius
before they are initialized. Because of this, it is safe to initialize
thermtrip and soctherm in any order.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Merge "Third Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:
* Special-case PM domains with memory-controllers
* tag 'renesas-soc3-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Special-case PM domains with memory-controllers
ARM: shmobile: R-Mobile: Generalize adding/looking up special PM domains
ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "Second Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:
* Add DT support for PM domains
* tag 'renesas-soc2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Add DT support for PM domains
ARM: shmobile: R-Mobile: Store SYSC base address in rmobile_pm_domain
ARM: shmobile: R-Mobile: Use generic_pm_domain.attach_dev() for pm_clk setup
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: STi: SoC changes for v3.20, round 1" from Maxime Coquelin:
Highlights:
-----------
- Add support for STiH418 SoC
* tag 'sti-soc-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti:
ARM: STi: Add STiH418 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "at91: cleanup for 3.20 #2" from Nicolas Ferre:
Second batch of cleanup for 3.20:
- By reworking the PM code, we can remove the AT91 more specific initialization
- We are using DT for SRAM initialization now, so we can remove its explicit
mapping
- The PMC clock driver now hosts IDLE function for at91rm9200 with other
SoCs ones.
* tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (37 commits)
ARM: at91: move at91rm9200_idle() to clk/at91/pmc.c
ARM: at91: remove unused at91_init_sram
ARM: at91: sama5d4: remove useless call to at91_init_sram
ARM: at91: remove useless map_io
ARM: at91: pm: prepare for multiplatform
ARM: at91: pm: add UDP and UHP checks to newer SoCs
ARM: at91: pm: use the mmio-sram pool to access SRAM
ARM: at91: pm: rework cpu detection
ARM: at91: dts: sama5d3: add ov2640 camera sensor support
ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK
ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}
ARM: at91: dts: sama5d3: move the isi mck pin to mb
ARM: at91: dts: sama5d3: add missing pins of isi
ARM: at91: dts: sama5d3: split isi pinctrl
ARM: at91: dts: sama5d3: add isi clock
ARM: at91/dt: ethernut5: use at91sam9xe.dtsi
ARM: at91/dt: Add a dtsi for at91sam9xe
ARM: at91/dt: add SRAM nodes
ARM: at91/dt: at91rm9200ek: enable RTC
ARM: at91/dt: rm9200: add RTC node
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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Enable smp for HiP01 board.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
[olof: split off the dts change to a separate commit]
Signed-off-by: Olof Johansson <olof@lixom.net>
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As hix5hd2 and hip01 has the same secondary_startup
so rename hix5hd2_secondary_startup to
to hisi_secondary_startup.
the hip01 will use hisi_secondary_startup for the
secondary core boot.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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As hix5hd2 and hip01 has the same .smp_prepare_cpus
in struct smp_operations, so rename hix5hd2_smp_prepare_cpus
to hisi_common_smp_prepare_cpus.
the hip01 will use hisi_common_smp_prepare_cpus in its
struct smp_operations.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Enable Hisilicon HiP01 SoC. This HiP01 SoC series support both
one core or dual cores and quad cores. The core is Cortex A9.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add the support of Hisilicon HiP01 debug uart.
The uart of hip01 is 8250 compatible.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "CSR new atlas7 machine, and delete old marco machine for 3.20" from
Barry Song:
drop CSR Marco machine and add Atlas7 new machine
This is the init support for CSR Atlas7 new SoC. Old Marco has never
shipped to customers and been dropped.
* tag 'new-atlas7mach-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: sirf: add Atlas7 machine support
ARM: sirf: move to debug_ll_io_init and drop map_io
ARM: sirf: move platsmp to support Atlas7 SoC
ARM: sirf: drop Marco machine
ARM: sirf: drop Marco support in reset controller module
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "CSR atlas7 debug ports for 3.20" from Barry Song:
add debug ports for CSRatlas7 SoC
Because Marco chip has never shipped to customers and has been replaced
by Atlas7, so we do the below
- drop Marco's debug port
- add debug ports for Atlas7
* tag 'atlas7-lldebug-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: sirf: add two debug ports for CSRatlas7 SoC
ARM: sirf: drop Marco low-level debug port
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Rockchip support is not limited to Cortex-A9 socs anymore and its
presence may confuse people reading /proc/cpuinfo. So remove the core
specific part.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
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This patch changes the description of the low-level-debug port. SoC mt8127 and
mt6592 have the same uart port and the same mapping. We just change the
description to add low-level-debug to mt6592.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Olof Johansson
Baruch Siach
Michal Simek
Moritz Fischer
Tony Lindgren
Aida Mynzhasova
Alexandre Belloni
Nicolas Ferre
Andy Gross
Stephen Boyd
Mikko Perttunen
Lina Iyer
Wang Long
Heiko Stuebner
Matthias Brugger