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path: root/drivers/gpu/drm/i915/display/intel_dpll.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-04-22drm/i915/display: pass struct intel_display to PCH macrosJani Nikula1-8/+3
2025-03-28drm/i915/dpll: convert intel_dpll.[ch] to struct intel_displayJani Nikula1-163/+149
2025-03-25drm/i915/lvds: convert intel_lvds.[ch] to struct intel_displayJani Nikula1-6/+7
2025-02-13drm/i915/display: convert assert_transcoder*() to struct intel_displayJani Nikula1-14/+16
2025-02-12drm/i915/dpll: Use intel_display for asserting pllSuraj Kandpal1-6/+5
2024-12-16drm/i915/uncore: add to_intel_uncore() and use itJani Nikula1-0/+1
2024-10-29drm/i915/display: convert I915_STATE_WARN() to struct intel_displayJani Nikula1-4/+5
2024-10-23drm/i915/panel: Convert panel code to intel_displayVille Syrjälä1-9/+18
2024-10-02drm/i915: remove IS_LP()Jani Nikula1-2/+5
2024-09-16drm/i915/display: fix typo in the commentYan Zhen1-1/+1
2024-09-05drm/i915/display: pass display to intel_crtc_for_pipe()Jani Nikula1-1/+2
2024-09-03drm/i915/pps: convert intel_pps.[ch] to struct intel_displayJani Nikula1-3/+6
2024-06-07drm/i915: pass dev_priv explicitly to DPLL_MDJani Nikula1-7/+11
2024-06-07drm/i915: pass dev_priv explicitly to DPLLJani Nikula1-22/+23
2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hVille Syrjälä1-0/+1
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä1-43/+42
2024-04-30drm/i915/dpio: s/pipe/ch/Ville Syrjälä1-24/+25
2024-04-30drm/i915/dpio: s/port/ch/Ville Syrjälä1-27/+27
2024-04-30drm/i915/dpio: Rename some variablesVille Syrjälä1-49/+48
2024-04-30drm/i915/dpio: Remove pointless variables from vlv/chv DPLL codeVille Syrjälä1-36/+28
2024-04-30drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä1-9/+9
2024-04-30drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/Ville Syrjälä1-1/+1
2024-04-30drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/Ville Syrjälä1-4/+4
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä1-1/+1
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä1-15/+16
2024-04-17drm/i915: Add local DPLL 'hw_state' variablesVille Syrjälä1-46/+56
2024-04-17drm/i915: s/pipe_config/crtc_state/ in legacy PLL codeVille Syrjälä1-15/+15
2024-04-17drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()Ville Syrjälä1-12/+9
2024-04-17drm/i915: Modernize i9xx_pll_refclk()Ville Syrjälä1-8/+7
2024-04-17drm/i915: Inline {i9xx,ilk}_update_pll_dividers()Ville Syrjälä1-33/+13
2024-04-17drm/i915: Extract {i9xx,i8xx,ilk,vlv,chv}_dpll()Ville Syrjälä1-33/+68
2024-04-17drm/i915: Extract i965_dpll_md()Ville Syrjälä1-9/+9
2024-04-17drm/i915: Extract i9xx_dpll_get_hw_state()Ville Syrjälä1-0/+30
2024-04-17drm/i915: Extract ilk_dpll_compute_fp()Ville Syrjälä1-10/+12
2024-04-17drm/i915: Extract ilk_fb_cb_factor()Ville Syrjälä1-15/+17
2023-11-17drm/i915: convert vlv_dpio_read()/write() from pipe to phyJani Nikula1-51/+55
2023-11-17drm/i915: move *_crtc_clock_get() to intel_dpll.cJani Nikula1-2/+173
2023-10-29drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi1-6/+1
2023-10-12drm/i915/display: Use correct method to free crtc_stateSuraj Kandpal1-1/+2
2023-08-24drm/i915: Fully populate crtc_state->dpllVille Syrjälä1-2/+15
2023-08-24drm/i915: Don't warn about zero N/P in *_calc_dpll_params()Ville Syrjälä1-17/+20
2023-06-07drm/i915/dpll: drop unused but set variables bestn and bestm1Jani Nikula1-3/+1
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula1-1/+1
2023-04-28drm/i915/mtl: C20 port clock calculationMika Kahola1-0/+2
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada1-1/+32
2023-01-18drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under stateJani Nikula1-1/+1
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-11-03drm/i915/dpio: un-inline the vlv phy/channel mapping functionsJani Nikula1-0/+1
2022-09-13drm/i915: Fix TV encoder clock computationVille Syrjälä1-2/+6
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä1-3/+57
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