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2016-11-28drm/msm: gpu: Add A5XX target supportJordan Crouse8-9/+945
Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Disable interrupts during initJordan Crouse2-0/+7
Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Remove 'src_clk' from adreno configurationJordan Crouse2-24/+14
The adreno code inherited a silly workaround from downstream from the bad old days before decent clock control. grp_clk[0] (named 'src_clk') doesn't actually exist - it was used as a proxy for whatever the core clock actually was (usually 'core_clk'). All targets should be able to correctly request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7Jordan Crouse1-0/+30
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Add adreno_gpu_write64()Jordan Crouse4-5/+34
Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and writes/reads from that register will be quietly dropped. This can be immediately put in place for the ringbuffer base and the RPTR address. Both writes are converted to use adreno_gpu_write64() with their respective high and low registers and the high register appropriately marked as SKIP for both 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu Add new gpu register read/write functionsJordan Crouse2-10/+41
Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Return error on hw_init failureJordan Crouse5-26/+30
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Cut down the list of "generic" registers to the ones we useJordan Crouse3-215/+0
There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: update generated headersRob Clark15-107/+4177
Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm/adreno: move scratch register dumping to per-gen codeRob Clark3-6/+14
Scratch registers move, annoyingly enough, in a5xx. Move to per-generation aNxx_recover() fxn. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm/rd: support for 64b iovaRob Clark1-2/+2
For backwards compat, the rd format puts the high 32b after the size field in the GPUADDR packet. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: convert iova to 64bRob Clark15-32/+34
For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: set dma_mask properlyRob Clark1-1/+7
Previous value really only made sense on armv7 without LPAE. Everything that supports more than 4g of memory also has iommu's that can map anything. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: Remove bad calls to of_node_put()Archit Taneja1-7/+2
In add_components_mdp, we parse the endpoints in MDP output ports using the helper for_each_endpoint_of_node(). Our function calls of_node_put() on the endpoint node before we iterate over the next one. This is already done by the helper, and results in trying to decrement the refcount twice. Remove the extra of_node_put calls. This fixes warnings seen when we try to insert the driver as a module on IFC6410. Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: move LM bounds check into plane->atomic_check()Rob Clark2-2/+15
The mode_config->max_{width,height} is for the maximum size of a fb, not the max scanout limits (of the layer-mixer). It is legal, and in fact common, to create a larger fb, only only scan-out a smaller part of it. For example multi-monitor configurations for x11, or android wallpaper layer (which is created larger than the screen resolution for fast scrolling by just changing the src x/y coordinates). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: dump smp state on errors tooRob Clark2-2/+6
If the dumpstate modparam is enabled, for debugging error irq's, also dump SMP state. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: add debugfs to show smp block statusRob Clark6-3/+116
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: handle SMP block allocations "atomically"Rob Clark7-245/+193
Previously, SMP block allocation was not checked in the plane's atomic_check() fxn, so we could fail allocation SMP block allocation at atomic_update() time. Re-work the block allocation to request blocks during atomic_check(), but not update the hw until committing the atomic update. Since SMP blocks allocated at atomic_check() time, we need to manage the SMP state as part of mdp5_state (global atomic state). This actually ends up significantly simplifying the SMP management, as the SMP module does not need to manage the intermediate state between assigning new blocks before setting flush bits and releasing old blocks after vblank. (The SMP registers and SMP allocation is not double-buffered, so newly allocated blocks need to be updated in kms->prepare_commit() released blocks in kms->complete_commit().) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: dynamically assign hw pipes to planesRob Clark6-80/+172
(re)assign the hw pipes to planes based on required caps, and to handle situations where we could not modify an in-use plane (ie. SMP block reallocation). This means all planes advertise the superset of formats and properties. Userspace must (as always) use atomic TEST_ONLY step for atomic updates, as not all planes may be available for use on every frame. The mapping of hwpipe to plane is stored in mdp5_state, so that state updates are atomically committed in the same way that plane/etc state updates are managed. This is needed because the mdp5_plane_state keeps a pointer to the hwpipe, and we don't want global state to become out of sync with the plane state if an atomic update fails, we hit deadlock/ backoff scenario, etc. The use of state_lock keeps multiple parallel updates which both re-assign hwpipes properly serialized. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: add skeletal mdp5_stateRob Clark2-0/+65
Add basic state duplication/apply mechanism. Following commits will move actual global hw state into this. The state_lock allows multiple concurrent updates to proceed as long as they don't both try to alter global state. The ww_mutex mechanism will trigger backoff in case of deadlock between multiple threads trying to update state. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2016-11-27drm/msm: subclass drm_atomic_stateRob Clark4-0/+51
This will give the kms backends a slot to stash their own hw specific global state. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: introduce mdp5_hw_pipeRob Clark7-87/+199
Split out the hardware pipe specifics from mdp5_plane. To start, the hw pipes are statically assigned to planes, but next step is to assign the hw pipes during plane->atomic_check() based on requested caps (scaling, YUV, etc). And then hw pipe re-assignment if required if required SMP blocks changes. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2016-11-27drm/msm/mdp5: rip out mode_changedRob Clark2-21/+4
It wasn't really doing the right thing if, for example, position or height changed. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: don't be so castyRob Clark1-5/+7
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: drop mdp5_plane::nameRob Clark1-15/+11
Just use plane->name now that it is a thing. In a following patch, once we dynamically assign hw pipes to planes, it won't make sense to name planes the way we do, so this also partly reduces churn in following patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: nuke mdp5_plane_complete_flip()Rob Clark3-23/+10
We can do this all from mdp5_plane_complete_commit(), so simplify things a bit and drop mdp5_plane_complete_flip(). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: drop mdp5_crtc::nameRob Clark1-17/+11
Plane's (pipes) can be assigned dynamically with atomic, so it doesn't make much sense to name the pipe after it's primary plane. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: small renameRob Clark1-4/+4
These are really plane-id's, not crtc-id's. Only connection to CRTCs is that they are used as primary-planes. Current name is just legacy from when we only supported RGB/primary planes. Lets pick a better name now. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: support multiple address spacesRob Clark16-80/+208
We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm/mdp5: clip img size to src sizeRob Clark1-2/+2
If fb dimensions are larger than what can be scanned out, but the src dimensions are not, the hw can still handle this. So clip. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm: use DRM_DEBUG_DRIVER()Rob Clark1-2/+2
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm/mdp5: 8x16 actually has 8 mixer stagesRob Clark1-1/+1
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm: update uapi header licenseRob Clark1-9/+16
The same file in libdrm is, as is the tradition with the rest of libdrm, etc, using an MIT license. To avoid complications in the future with sync'ing the uapi header to libdrm, lets fix the license mismatch now before there are any non-trivial commits from someone other than myself. Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Gabriel Laskar <gabriel@lse.epita.fr> Cc: Mikko Rapeli <mikko.rapeli@iki.fi> Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-26drm/msm/mdp5: no scaling support on RGBn pipes for 8x16Rob Clark2-7/+4
Looks like cut/paste error from the other device cfgs (which do support scaling on RGBn pipes). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm/mdp5: handle non-fullscreen base plane caseRob Clark1-18/+28
If the bottom-most layer is not fullscreen, we need to use the BASE mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT). The blend_setup() code pretty much handled this already, we just had to figure this out in _atomic_check() and assign the stages appropriately. Also fix the case where there are zero enabled planes, where we also need to enable BORDER_OUT. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-18drm/i2c: tda998x: fix spelling mistakeColin Ian King1-1/+1
Trivial fix to spelling mistake "configutation" to "configuration" in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: allow sharing of the CEC device accessesRussell King1-19/+34
cec_read() is non-atomic in the presence of other I2C bus transactions to the same device. This presents a problem when we add support for the TDA9950 CEC engine part - both drivers can be trying to access the device. Avoid the inherent problems by switching to i2c_transfer() instead, which allows us to perform more than one bus transaction atomically. As this means we will be using I2C transactions rather than SMBUS, we have to check that the host supports I2C functionality. Tested-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: allow interrupt to be sharedRussell King1-25/+27
Some TDA998x contain several different I2C devices - there is the HDMI encoder, and there is a TDA9950 CEC engine. These two share the same interrupt signal. In order to allow a driver for the CEC engine to work, we need to be able to share the interrupt with the CEC driver, so convert the handler and registration to allow this to happen. Tested-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: power down pre-filter and color conversionRussell King1-0/+4
Disabling the pre-filter block of the TDA998x saves 40mW and the colour conversion block saves 15mW. As we always disable these two blocks, we can power these sections of the chip down to save 55mW of unnecessary power consumption. Tested-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: switch to boolean is_onRussell King1-13/+10
Rather than storing the DPMS mode (which will always be on or off) use a boolean to store this instead. Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: remove complexity from tda998x_audio_get_eld()Russell King1-14/+8
tda998x_audio_get_eld() is needlessly complex - the connector associated with the encoder is always our own priv->connector. Remove this complexity, but ensure that there are no races when copying out the ELD. Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: group audio functions togetherRussell King1-137/+139
Group the TDA998x audio functions together rather than split between two different locations in the file, keeping like code together. Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: separate connector initialisationRussell King1-20/+26
Separate out the connector initialisation from the rest of the drivers initialisation. Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: group connector functions and funcs togetherRussell King1-174/+176
Group the TDA998x connector functions and funcs structures together before the encoder support, rather than scattered amongst the rest of the file. This keeps like code together. Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: move and rename tda998x_encoder_set_config()Russell King1-20/+20
The naming of tda998x_encoder_set_config() is a left-over from when TDA998x was a slave encoder. Since this is part of the initialisation, drop the _encoder from the name, and move it near tda998x_bind(). Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: correct function name in commentsRussell King1-2/+2
Correct two references to tda998x_connector_get_modes() which were incorrectly referring to tda998x_encoder_get_modes(). Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: only enable audio if supported by sinkRussell King1-3/+24
Check for audio support by the attached sink by consulting the EDID prior to enabling audio over the TMDS link. We must consult the EDID after calling drm_helper_probe_single_connector_modes(), as this can use an override EDID, or load a replacement EDID. Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: only configure infoframes and audio if supportedRussell King1-5/+19
The CEA 861B specification indicates the situations when we are able to send each infoframe based on the version of the EDID's CEA extension. Update the tda998x driver to follow the CEA specification wrt sending of infoframes. Since we only support the generation of AVI version 2, this limits us to CEA extension version 3, so we treat CEA extension version 2 as CEA 861 (no infoframes, no audio.) Tested-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: avoid race when programming audioRussell King1-2/+2
Avoid a race between programming audio and an in-progress mode set. A mode set is complex, and disables the ability to send infoframes to the sink, and is disruptive to audio - we have to mute the audio FIFO while doing a mode set. If an attempt is made to start up the audio side, we will undo the audio FIFO mute before the mode set has completed. Move the lock so that we prevent audio interfering with an in-progress mode set. Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2016-11-18drm/i2c: tda998x: avoid racy access to mode clockRussell King1-14/+11
Avoid a racy access to the mode clock by storing the current mode clock during a mode set under the audio mutex. This allows us to access it from the audio path in a safe way. Tested-by: Jon Medhurst <tixy@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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