aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/call-graph-from-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2016-03-16drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZEric Huang1-0/+5
Set the UVD and VCE DPM flags otherwise UVD and VCE DPM won't get enabled. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Cc: stable@vger.kernel.org
2016-03-16drm/amdgpu: switch back to 32bit hw fences v2Christian König2-32/+21
We don't need to extend them to 64bits any more, so avoid the extra overhead. v2: update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: remove amdgpu_fence_is_signaledChristian König1-25/+0
It's just overhead to check the fence value when we signal them directly anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: drop the extra fence range check v2Christian König1-3/+0
Amdgpu doesn't support using scratch registers for fences any more. So we won't see values like 0xdeadbeef as fence value any more. v2: reschedule timer even if no change detected Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: signal fences directly in amdgpu_fence_processChristian König2-68/+31
Because of the scheduler we need to signal all fences immediately anyway, so try to avoid the waitqueue overhead. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: cleanup amdgpu_fence_wait_empty v2Christian König1-54/+15
Just wait for last fence instead of waiting for the sequence manually. v2: don't use amdgpu_sched_jobs for the mask Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: keep all fences in an RCU protected array v2Christian König2-3/+31
Just keep all HW fences in a RCU protected array as a first step to replace the wait queue. v2: update commit message, move fixes into separate patch. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ringChristian König3-4/+12
Make this a parameter instead of using the global variable directly. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: RCU protected amd_sched_fence_releaseChristian König1-1/+22
Fences must be freed RCU protected, otherwise the reservation_object_*_rcu() functions can run into problems. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-16drm/amdgpu: RCU protected amdgpu_fence_releaseChristian König1-1/+22
Fences must be freed RCU protected, otherwise the reservation_object_*_rcu() functions can run into problems. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-16drm/amdgpu: merge amdgpu_fence_process and _activityChristian König1-19/+5
No need to keep the two separate any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-16drm/amdgpu: cleanup amdgpu_fence_activityChristian König1-32/+3
The comment about the loop counter was never valid, even when you have multiple threads this loop only runs as long as the sequence increases. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-14drm/amdgpu: move fence structure into amdgpu_fence.cChristian König2-26/+25
No need to have that in the header file any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: remove amdgpu_fence_wait_nextChristian König2-21/+0
Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: remove amdgpu_ring_from_fenceChristian König2-25/+0
Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: stop using the ring index in the SAChristian König2-36/+22
The ring index will always collide as hash into the fence list, so use the context number instead. That can still cause collisions, but they are less likely than using ring indices. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: stop waiting on UVD messages before mapping themChristian König1-7/+0
amdgpu_bo_kmap() now always waits for moves to finish. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: always wait before kmap a BOChristian König1-5/+11
When a BO is currently moving we otherwise would blindly access the new location without checking. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/radeon: refactor SI tiling table initializationJosh Poimboeuf1-486/+439
Simplify the control flow of si_tiling_mode_table_init() similar to how it was done in gfx_v7_0.c and gfx_v8_0.c. Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/radeon: refactor CIK tiling table initializationJosh Poimboeuf1-1025/+666
Simplify the control flow of cik_tiling_mode_table_init() similar to how it was done in gfx_v7_0.c and gfx_v8_0.c. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amdgpu: allow write access to mapped userptrsChristian König1-5/+3
With the updated MMU notifier we should also be able to handle the writeback case correctly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amd/powerplay: use pp_endian.h for TongaAlex Deucher1-11/+1
Drop local versions of these macros. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14drm/amd/powerplay: use pp_endian.h for FijiAlex Deucher1-11/+1
Drop local versions of these macros. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>