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2018-10-02MAINTAINERS: fix pattern in ARM/Synaptics berlin SoC sectionJisheng Zhang1-2/+2
Berlin SoC files has been moved from marvell dir to synaptics dir, but commit bc52497a595d ("MAINTAINERS: update entry for ARM/berlin") didn't update the dir accordingly. This patch fixes it. From another side, new derivative SoCs from Synaptics may not be named as berlin*, so let's update the entries accordingly. Fixes: bc52497a595d ("MAINTAINERS: update entry for ARM/berlin") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Reported-by: Joe Perches <joe@perches.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02MAINTAINERS: Drop dt-bindings/genpd/k2g.hNishanth Menon1-1/+0
Drop include/dt-bindings/genpd/k2g.h which disappeared from kernel tree some time back, however MAINTAINERS file was missed to be updated. Fixes: d16645054d2f ("dt-bindings: Drop k2g genpd device ID macros") Cc: Rob Herring <robh@kernel.org> Cc: Dave Gerlach <d-gerlach@ti.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Reported-by: Joe Perches <joe@perches.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-30arm64: actions: Enable PINCTRL in platforms KconfigManivannan Sadhasivam1-0/+1
Select PINCTRL for Actions Semi SoCs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30MAINTAINERS: Add entry for Actions Semi Owl SoCs DMA driverManivannan Sadhasivam1-0/+2
Add entry for Actions Semi Owl SoCs DMA driver under ARM/ACTIONS. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30MAINTAINERS: Add entry for Actions Semiconductor Owl I2C driverManivannan Sadhasivam1-0/+2
Add entry for Actions Semiconductor Owl I2C driver under ARM/ACTIONS. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30MAINTAINERS: Update clock binding entry for Actions Semi Owl SoCsManivannan Sadhasivam1-1/+1
commit d0e45d686a3e ("dt-bindings: clock: Add S700 support for Actions Semi Soc's")' renamed the clock binding for Actions Semi Owl SoCs from actions,s900-cmu.txt to actions,owl-cmu.txt inorder to accommodate all members of Owl family SoCs. Hence, update the relevant entry in MAINTAINERS file. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30ARM: imx: add i.mx6ulz msl supportAnson Huang4-2/+32
The i.MX 6ULZ processor is a high-performance, ultra cost-efficient consumer Linux processor featuring an advanced implementation of a single Arm® Cortex®-A7 core, which operates at speeds up to 900 MHz. This patch adds basic MSL support for i.MX6ULZ, the i.MX6ULZ has same soc_id as i.MX6ULL, and SRC_SBMR2 bit[6] is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means i.MX6ULZ and 1'b0 means i.MX6ULL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-28ARM: Assume maintainership of ARM reference designsLinus Walleij1-0/+37
With this I assume maintainership of the Integrator, Versatile and RealView ARM reference machines. It's no big secret that I've been maintaining them for years, but might as well make it official so I get the mails and don't miss anything. I have also included some drivers that are closely associated with the ARM reference designs and yet orphaned in the MAINTAINERS file. I can surely maintain them too, or route the question to the right people so it doesn't fall on the floor of upward to the subsystem maintainers who have too much to do already as it is. Cc: Russell King <linux@armlinux.org.uk> Cc: Rob Herring <robh@kernel.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Brian Norris <computersforpeace@gmail.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28ARM: support big-endian for the virt architectureJason A. Donenfeld1-0/+1
This architecture, used for running in QEMU, runs just fine when compiled in big-endian mode. So enable it. This is enabled in exactly the same way that it is for other platforms (such as vexpress) that also support big-endian mode in QEMU successfully. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-25MAINTAINERS: sdhci: move the Microchip entry to proper locationNicolas Ferre1-6/+6
All SDHCI controller drivers are gathered at the same place, add the Microchip one there. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: move former ATMEL entries to proper MICROCHIP locationNicolas Ferre1-77/+77
Standardize the Microchip / Atmel entries with the same form and move them so that they are all located at the same place, under the newer MICROCHIP banner. Only modifications to the titles of the entries are done in this patch. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: remove the / ATMEL string from MICROCHIP entriesNicolas Ferre1-11/+11
No need to keep this additional string as it can puzzle people while adding new driver's entries. Move the NAND entry to keep it alphabetically ordered. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: iio: add co-maintainer to SAMA5D2-compatible ADC driverNicolas Ferre1-0/+3
Add Eugen as co-maintainer with Ludovic of Microchip SAMA5D2-compatible ADC driver. Also add the binding documentation/include as file pattern. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: pwm: add entry for Microchip pwm driverNicolas Ferre1-0/+8
Add the entry that was missing for pwm-atmel.c driver. Add binding file as well. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: dmaengine: add files to Microchip dma entryNicolas Ferre1-0/+2
In Microchip DMA (HDMA actually) entry, add the missing files for better matching with get_maintainer.pl tool. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: USB: change maintainer for Microchip USBA gadget driverNicolas Ferre1-1/+1
Hand over this USB gadget driver to Cristian: atmel_usba. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: ASoC: change maintainer for Microchip ALSA driversNicolas Ferre1-1/+1
Hand over to Codrin for Microchip Audio SoC drivers in "atmel" directory. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: media: change Microchip ISI, ISC maintainersNicolas Ferre1-2/+2
For ISC, Songjun is not with Microchip anymore, his address shouldn't be reachable. For ISI, Eugen can handle the maintenance now. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: update entry for Microchip NAND driver supportNicolas Ferre1-1/+1
Replace the Microchip/Atmel NAND controller driver maintainer by removing Josh and adding Tudor. Cc: Josh Wu <rainyfeeling@outlook.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25MAINTAINERS: ARM: at91: add co-maintainer for ARM/MicrochipNicolas Ferre1-1/+2
Add Ludovic as a new co-maintainer for the AT91 Microchip ARM sub-architecture. Add the newly created kernel.org group git tree that we will use from now on. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-25ARM: at91: pm: call put_device instead of of_node_put in at91_pm_config_wszhong jiang1-3/+3
of_find_device_by_node takes a reference to the struct device when it finds a match via get_device. but it fails to put_device in at91_pm_config_ws, for_each_matching_node_and_match will get and put the node properly, there is no need to call the of_put_node. Therefore, just call put_device instead of of_node_put in at91_pm_config_ws. Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode") Suggested-by: Claudiu Beznea <Claudiu.Beznea@microchip.com> Signed-off-by: zhong jiang <zhongjiang@huawei.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-24dt-bindings: marvell,prestera: Add common compatible stringChris Packham1-2/+2
Add "marvell,prestera" as a compatible string so that drivers can be written to account for any prestera variant without needing to specialise to the more specific values. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-24MAINTAINERS: replace free-electrons.com by bootlin.com for Thomas PetazzoniThomas Petazzoni1-4/+4
Free Electrons is now called Bootlin, and my e-mail address was changed as well, so this commit updates the entries in the MAINTAINERS file accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-24ARM: mvebu: use dt_fixup to provide fallback for enable-methodChris Packham1-6/+8
We need to maintain backwards compatibility with device trees that don't define an enable method. At the same time we want the device tree to be able to specify an enable-method and have it stick. Previously by having smp assigned in the DT_MACHINE definition this would be picked up by setup_arch() and override whatever arm_dt_init_cpu_maps() had configured. Now we move the initial assignment of default smp_ops to a dt_fixup and let arm_dt_init_cpu_maps() override that if the device tree defines an enable-method. [olof@lixom.net: Wrap set_smp_ops() in CONFIG_SMP.] Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> (on AX3) Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-23MAINTAINERS: Update stm32 entryBenjamin Gaignard1-0/+2
Add mailing list for stm32 architecture. Add "stm" pattern to not miss some drivers/directories when asking for maintainers. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-09-22MAINTAINERS: Add Actions Semi S900 clk entriesManivannan Sadhasivam1-0/+2
Add S900 clk entries under ARCH_ACTIONS. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-22MAINTAINERS: Add reviewer for ACTIONS platformsManivannan Sadhasivam1-0/+1
Since I'll be working on improving support for ACTIONS platforms, adding myself as the reviewer. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-20ARM: OMAP1: ams-delta: Don't request unused GPIOsJanusz Krzysztofik1-39/+1
GPIOs with no kernel drivers can still be used from user space, don't request them from the board file. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-20ARM: OMAP1: ams-delta-fiq: Use <linux/platform_data/gpio-omap.h>Janusz Krzysztofik2-9/+7
Instead of defining symbols already defined in linux/platform_data/gpio-omap.h, use that header file. Since we include the header into an assembler code, prevent C only bits from being read in. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-20ARM: OMAP1: ams-delta: register MODEM device earlierJanusz Krzysztofik1-4/+18
Amstrad Delta MODEM device used to be initialized at arch_initcall before it was once moved to late_initcall by commit f7519d8c8290 ("ARM: OMAP1: ams-delta: register latch dependent devices later"). The purpose of that change was to postpone initialization of devices which depended on latch2 pins until latch2 converted to GPIO device was ready. After recent fixes to GPIO handling, it was possible to moove registration of most of those device back to where they were before. The same can be safely done with the MODEM device as initialization of GPIO pins it depends on was moved to machine_init by preceding patch. Move registration of the MODEM device to arch_initcall_sync, not to arch_initcall, so it is never exposed to potential conflict in registration order hazard against OMAP serial ports. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-20ARM: OMAP1: ams-delta: initialize latch2 pins to safe valuesJanusz Krzysztofik2-24/+35
Latch2 pins control a number of on-board devices, namely LCD, NAND, MODEM and CODEC. Those pins used to be initialized with safe values from init_machine before that operation was: 1) moved to late_initcall in preparation for conversion of latch2 to GPIO device - see commit f7519d8c8290 ("ARM: OMAP1: ams-delta: register latch dependent devices later"), 2) replaced with non-atomic initialization performed by means of gpio_request_array() - see commit 937eb4bb0058 ("ARM: OMAP1: ams-delta: convert latches to basic_mmio_gpio"), 3) made completely asynchronous by delegation of GPIO request operations performed on subsets of pins to respective device drivers in subsequent commits. One visible negative result of that disintegration was corrupt keyboard data reported by serio driver, recently fixed by commit 41f8fee385a0 ("ARM: OMAP1: ams-delta: Hog "keybrd_dataout" GPIO pin"). Moreover, initialization of LATCH2_PIN_MODEM_CODEC still performed with ams_delta_latch2_write() wrapper from late_init() is now done on not requested GPIO pin. Reintroduce atomic initialization of latch2 pins at machine_init to prevent from random values potentially corrupting NAND data or maybe even destroing other hardware. Also take care of MODEM/CODEC related pins so MODEM device probe succeeds even if latch2 GPIO device or dependent regulator is not ready and CODEC can be reached over the MODEM even if audio driver doesn't take control over LATCH2_PIN_MODEM_CODEC. Once done, remove the no longer needed GPIO based implementation of ams_delta_latch_write() and its frontend macro. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [tony@atomide.com: updated for the header location to remove dependency] Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-20ARM: OMAP1: ams-delta: assign MODEM IRQ from GPIO descriptorJanusz Krzysztofik1-12/+35
Don't request MODEM IRQ GPIO by its global number in ams_delta_modem_init(). Instead, obtain its GPIO descriptor and assign related IRQ to the MODEM. Do that from omap_gpio_deps_init(), where the chip is already looked up. Then, in ams_delta_modem_init(), just check for the IRQ number having been already assigned. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-19ARM: shmobile: Rework the PMIC IRQ line quirkMarek Vasut1-29/+110
Rather than hard-coding the quirk topology, which stopped scaling, parse the information from DT. The code looks for all compatible PMICs -- da9063 and da9210 -- and checks if their IRQ line is tied to the same pin. If so, the code sends a matching sequence to the PMIC to deassert the IRQ. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> (on Koelsch) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-19ARM: debug-ll: Add support for r8a7744Biju Das1-4/+5
Enable low-level debugging support for RZ/G1N (R8A7744). RZ/G1N uses SCIF0 for the debug console. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-17ARM: shmobile: r8a7744: Basic SoC supportBiju Das2-0/+7
Add minimal support for the RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-12ARM: imx6: register pm_power_off handler if "fsl,pmic-stby-poweroff" is setOleksij Rempel1-0/+25
One of the Freescale recommended sequences for power off with external PMIC is the following: ... 3. SoC is programming PMIC for power off when standby is asserted. 4. In CCM STOP mode, Standby is asserted, PMIC gates SoC supplies. See: http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf page 5083 This patch implements step 4. of this sequence. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-11arm64: Add Renesas R8A774C0 supportFabrizio Castro1-0/+6
Add configuration option for the RZ/G2E (R8A774C0) SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11arm64: Add Renesas R8A774A1 supportBiju Das1-0/+6
Add configuration option for the RZ/G2M (R8A774A1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11ARM: shmobile: convert to SPDX identifiersKuninori Morimoto11-59/+14
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-10ARM: imx: add mmdc ipg clock operation for mmdcAnson Huang1-0/+14
i.MX6 SoCs have MMDC ipg clock for registers access, to make sure MMDC registers access successfully, add optional clock enable for MMDC driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-07ARM: OMAP2+: Convert to using %pOFn instead of device_node.nameRob Herring1-8/+8
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> [tony@atomide.com: updated against clkctrl and rt_idx changes] Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-07ARM: OMAP2+: hwmod_core: improve the support for clkctrl clocksTero Kristo1-29/+43
This patch adds support for split memory ranges for clkctrl providers. This is necessary to support the coming clockdomain based split of clkctrl provider ranges, instead of the current CM instance based one. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-06ARM: u300: Delete dummy SPI chipLinus Walleij3-290/+0
It's been told to me a few times that this kernel module should not exist, instead we should use the loopback test from userspace if need be. If a kernel module is required for testing SPI, it should be generic and put in drivers/spi/*. Delete this driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-09-06arm64: enable CMT/TMU support for Renesas SoCSergei Shtylyov1-0/+2
Renesas R-Car gen3 SoCs have both CMT and TMU timers, so we have to enable building them in Kconfig.platforms (as they don't normally have the prompts in Kconfig). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-05ARM: zynq: Convert to using %pOFn instead of device_node.nameRob Herring1-1/+1
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Michal Simek <michal.simek@xilinx.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-02Linux 4.19-rc2Linus Torvalds1-1/+1
2018-09-02x86/pti: Fix section mismatch warning/errorRandy Dunlap1-1/+1
Fix the section mismatch warning in arch/x86/mm/pti.c: WARNING: vmlinux.o(.text+0x6972a): Section mismatch in reference from the function pti_clone_pgtable() to the function .init.text:pti_user_pagetable_walk_pte() The function pti_clone_pgtable() references the function __init pti_user_pagetable_walk_pte(). This is often because pti_clone_pgtable lacks a __init annotation or the annotation of pti_user_pagetable_walk_pte is wrong. FATAL: modpost: Section mismatches detected. Fixes: 85900ea51577 ("x86/pti: Map the vsyscall page if needed") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andy Lutomirski <luto@kernel.org> Link: https://lkml.kernel.org/r/43a6d6a3-d69d-5eda-da09-0b1c88215a2a@infradead.org
2018-09-01x86/vdso: Fix lsl operand orderSamuel Neves1-1/+1
In the __getcpu function, lsl is using the wrong target and destination registers. Luckily, the compiler tends to choose %eax for both variables, so it has been working so far. Fixes: a582c540ac1b ("x86/vdso: Use RDPID in preference to LSL when available") Signed-off-by: Samuel Neves <sneves@dei.uc.pt> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Andy Lutomirski <luto@kernel.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20180901201452.27828-1-sneves@dei.uc.pt
2018-09-01x86/mce: Fix set_mce_nospec() to avoid #GP faultLuckTony1-1/+24
The trick with flipping bit 63 to avoid loading the address of the 1:1 mapping of the poisoned page while the 1:1 map is updated used to work when unmapping the page. But it falls down horribly when attempting to directly set the page as uncacheable. The problem is that when the cache mode is changed to uncachable, the pages needs to be flushed from the cache first. But the decoy address is non-canonical due to bit 63 flipped, and the CLFLUSH instruction throws a #GP fault. Add code to change_page_attr_set_clr() to fix the address before calling flush. Fixes: 284ce4011ba6 ("x86/memory_failure: Introduce {set, clear}_mce_nospec()") Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Anvin <hpa@zytor.com> Cc: Borislav Petkov <bp@alien8.de> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Link: https://lkml.kernel.org/r/20180831165506.GA9605@agluck-desk
2018-08-31x86/efi: Load fixmap GDT in efi_call_phys_epilog()Joerg Roedel1-6/+2
When PTI is enabled on x86-32 the kernel uses the GDT mapped in the fixmap for the simple reason that this address is also mapped for user-space. The efi_call_phys_prolog()/efi_call_phys_epilog() wrappers change the GDT to call EFI runtime services and switch back to the kernel GDT when they return. But the switch-back uses the writable GDT, not the fixmap GDT. When that happened and and the CPU returns to user-space it switches to the user %cr3 and tries to restore user segment registers. This fails because the writable GDT is not mapped in the user page-table, and without a GDT the fault handlers also can't be launched. The result is a triple fault and reboot of the machine. Fix that by restoring the GDT back to the fixmap GDT which is also mapped in the user page-table. Fixes: 7757d607c6b3 x86/pti: ('Allow CONFIG_PAGE_TABLE_ISOLATION for x86_32') Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Michal Hocko <mhocko@suse.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: hpa@zytor.com Cc: linux-efi@vger.kernel.org Link: https://lkml.kernel.org/r/1535702738-10971-1-git-send-email-joro@8bytes.org
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