aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/export-to-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2019-10-21clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()Geert Uytterhoeven1-8/+14
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190830134515.11925-8-geert+renesas@glider.be
2019-10-21clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()Geert Uytterhoeven1-10/+13
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clock on R-Car Gen2 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190830134515.11925-7-geert+renesas@glider.be
2019-10-07clk: renesas: r8a774b1: Add TMU clockBiju Das1-0/+5
This patch adds the TMU clocks to the R8A774B1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569249688-15821-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01clk: renesas: cpg-mssr: Add r8a774b1 supportBiju Das5-0/+335
Add RZ/G2N (R8A774B1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.4d of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.80, May 2019)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-7-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 bindingBiju Das1-4/+6
Add binding documentation for the RZ/G2N (R8A774b1) Clock Pulse Generator driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-6-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()Geert Uytterhoeven1-4/+8
cpg_sd_clock_round_rate() really needs the best rate, not the best divider. Hence change the iteration to find the former, and get rid of the final division. Add an out-of-range rate check while at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-6-geert+renesas@glider.be
2019-10-01clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()Geert Uytterhoeven1-14/+5
cpg_sd_clock_round_rate() is the sole caller of cpg_sd_clock_calc_div(), hence absorb the latter into the former. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-5-geert+renesas@glider.be
2019-10-01clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()Geert Uytterhoeven1-3/+3
The .set_rate() callback for the SD clocks is always called with a valid clock rate, returned by .round_rate(). Hence there is no need to iterate through the divider table twice: once to repeat the work done by .round_rate(), and a second time to find the corresponding divider entry. Just iterate once, looking for the divider that matches the passed clock rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be
2019-10-01clk: renesas: rcar-gen3: Improve arithmetic divisionsGeert Uytterhoeven1-2/+2
- Use div64_ul() instead of div_u64() if the divisor is unsigned long, to avoid truncation to 32-bit on 64-bit platforms, - Use div_u64() for 64-by-32 divisions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-3-geert+renesas@glider.be
2019-10-01clk: renesas: rcar-gen2: Improve arithmetic divisionsGeert Uytterhoeven1-3/+3
- Use div64_ul() instead of div_u64() if the divisor is unsigned long, to avoid truncation to 32-bit on 64-bit platforms, - Prefer ULL constant suffixes over casts to u64, - Prioritize multiplication over division, to increase accuracy. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-2-geert+renesas@glider.be
2019-10-01clk: renesas: Remove R-Car Gen2 legacy DT clock supportGeert Uytterhoeven3-478/+0
As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files use the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Hence remove backward compatibility with old R-Car Gen2 device trees describing a hierarchical representation of the various CPG and MSTP clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190830133615.11274-1-geert+renesas@glider.be
2019-10-01clk: renesas: mstp: Delete unnecessary kfree() in cpg_mstp_clocks_init()Markus Elfring1-3/+1
A NULL pointer would be passed to a call of the function kfree() directly after a call of the function kzalloc() failed at one place. Remove this superfluous function call. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Link: https://lore.kernel.org/r/e66b822b-026b-29cc-e461-6334aafd1d30@web.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>