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2024-06-28dmaengine: sh: rz-dmac: Fix lockdep assert warningBiju Das1-1/+1
Fix the below lockdep assert warning by holding vc.lock for vchan_get_all_descriptors(). WARNING: virt-dma.h:188 rz_dmac_terminate_all pc : rz_dmac_terminate_all Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240625170119.173595-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-21Documentation: dmaengine: Document new dma_vec APIPaul Cercueil2-0/+19
Document the dmaengine_prep_peripheral_dma_vec() API function, the device_prep_peripheral_dma_vec() backend function, and the dma_vec struct. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20240620122726.41232-8-paul@crapouillou.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-21dmaengine: dma-axi-dmac: Implement device_prep_peripheral_dma_vecPaul Cercueil1-0/+40
Add implementation of the .device_prep_peripheral_dma_vec() callback. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Co-developed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20240620122726.41232-3-paul@crapouillou.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-21dmaengine: Add API function dmaengine_prep_peripheral_dma_vec()Paul Cercueil1-0/+33
This function can be used to initiate a scatter-gather DMA transfer, where the address and size of each segment is located in one entry of the dma_vec array. The major difference with dmaengine_prep_slave_sg() is that it supports specifying the lengths of each DMA transfer; as trying to override the length of the transfer with dmaengine_prep_slave_sg() is a very tedious process. The introduction of a new API function is also justified by the fact that scatterlists are on their way out. Note that dmaengine_prep_interleaved_dma() is not helpful either in that case, as it assumes that the address of each segment will be higher than the one of the previous segment, which we just cannot guarantee in case of a scatter-gather transfer. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Co-developed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20240620122726.41232-2-paul@crapouillou.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: qcom: gpi: clean up the IRQ disable/enable in gpi_reset_chan()Dan Carpenter1-3/+2
The calls write_lock/unlock_irq() disables and re-enables the IRQs. Calling spin_lock_irqsave() and spin_lock_restore() when the IRQs are already disabled doesn't do anything and just makes the code confusing. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/8be473eb-65e0-42b4-b574-e61c3a7f62d8@moroto.mountain Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: fsl-edma: change the memory access from local into remote mode in i.MX 8QMJoy Zou3-1/+5
Fix the issue where MEM_TO_MEM fail on i.MX8QM due to the requirement that both source and destination addresses need pass through the IOMMU. Typically, peripheral FIFO addresses bypass the IOMMU, necessitating only one of the source or destination to go through it. Set "is_remote" to true to ensure both source and destination addresses pass through the IOMMU. iMX8 Spec define "Local" and "Remote" bus as below. Local bus: bypass IOMMU to directly access other peripheral register, such as FIFO. Remote bus: go through IOMMU to access system memory. The test fail log as follow: [ 66.268506] dmatest: dma0chan0-copy0: result #1: 'test timed out' with src_off=0x100 dst_off=0x80 len=0x3ec0 (0) [ 66.278785] dmatest: dma0chan0-copy0: summary 1 tests, 1 failures 0.32 iops 4 KB/s (0) Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Joy Zou <joy.zou@nxp.com> Cc: stable@vger.kernel.org Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240510030959.703663-1-joy.zou@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: qcom: gpi: remove unused struct 'reg_info'Dr. David Alan Gilbert1-6/+0
'reg_info' was never used since it's initial commit 5d0c3533a19f ("dmaengine: qcom: Add GPI dma driver") Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240517234024.231477-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: moxart-dma: remove unused struct 'moxart_filter_data'Dr. David Alan Gilbert1-5/+0
Remove unused struct 'moxart_filter_data' Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240516152825.262578-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dt-bindings: fsl-qdma: Convert to yaml formatFrank Li2-58/+124
Convert binding doc from txt to yaml. Re-order interrupt-names to align example. Add #dma-cell in example. Change 'reg' in example to 32bit address. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240528163734.2471268-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: fsl-edma: remove redundant "idle" field from fsl_chanFrank Li4-11/+2
The 'idle' in fsl_chan is redundant as it's equivalent to 'status != DMA_IN_PROGRESS'. So remote it to simple code logic. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240603152317.69917-2-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: fsl-edma: request per-channel IRQ only when channel is allocatedFrank Li3-14/+31
The edma feature individual IRQs for each DMA channel at some devices. Given the presence of numerous eDMA instances, each with multiple channels, IRQ request during probe results in an extensive list at /proc/interrupts. However, a significant portion of these channels remains unused by the system. Request irq only when a DMA client driver requests a DMA channel. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240603152317.69917-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: stm32-dma3: defer channel registration to specify channel nameAmelie Delaunay1-5/+14
On STM32 DMA3, channels can be reserved, so they are non available for Linux. This non-availability creates a mismatch between dma_chan id and DMA3 channel id. Use dma_async_device_channel_register() to register the channels after controller registration and change the default channel name, so that it can match the name in the Reference Manual and ease requesting a channel thanks to its name. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-12-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: add channel device name to channel registrationAmelie Delaunay3-8/+13
Channel device name is used for sysfs, but also by dmatest filter function. With dynamic channel registration, channels can be registered after dma controller registration. Users may want to have specific channel names. If name is NULL, the channel name relies on previous implementation, dma<controller_device_id>chan<channel_device_id>. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-11-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: stm32-dma3: improve residue granularityAmelie Delaunay1-2/+163
Implement own device_tx_status ops to compute the residue with a finer granularity, up to bytes. STM32 DMA3 has a bitfield, BNDT, in CxTR1 register which reflects the number of bytes read from the source. It also has a bitfield, FIFOL, in CxSR register which reflects the FIFO level in units of programmed destination data width. The channel is briefly suspended to get a coherent snapshot of registers. It is possible to correct the fifo level when packing/unpacking is enabled with destination increment. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-10-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: stm32-dma3: add device_pause and device_resume opsAmelie Delaunay1-0/+31
STM32 DMA3 controller is able to suspend an ongoing transfer (the transfer is suspended after the ongoing burst is flushed to the destination) and resume it from the point it was suspended. No need to reconfigure any register. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-9-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: stm32-dma3: add DMA_MEMCPY capabilityAmelie Delaunay1-1/+130
Add DMA_MEMCPY capability and relative device_prep_dma_memcpy ops with stm32_dma3_prep_dma_memcpy(). It reuses stm32_dma3_chan_prep_hw() and stm32_dma3_prep_hwdesc() helpers. As this driver relies on both device_config and of_xlate ops to pre-configure the channel for transfer, add a new helper (stm32_dma3_init_chan_config_for_memcpy) in case the channel is used without being pre-configured (with DT and/or dmaengine_slave_config()). Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-8-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: stm32-dma3: add DMA_CYCLIC capabilityAmelie Delaunay1-0/+77
Add DMA_CYCLIC capability and relative device_prep_dma_cyclic ops with stm32_dma3_prep_dma_cyclic(). It reuses stm32_dma3_chan_prep_hw() and stm32_dma3_chan_prep_hwdesc() helpers. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-7-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-11dmaengine: Add STM32 DMA3 supportAmelie Delaunay3-0/+1451
STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3 controller: - LPDMA (Low Power): 4 channels, no FIFO - GPDMA (General Purpose): 16 channels, FIFO from 8 to 32 bytes - HPDMA (High Performance): 16 channels, FIFO from 8 to 256 bytes Hardware configuration of the channels is retrieved from the hardware configuration registers. The client can specify its channel requirements through device tree. STM32 DMA3 channels can be individually reserved either because they are secure, or dedicated to another CPU. Indeed, channels availability depends on Resource Isolation Framework (RIF) configuration. RIF grants access to buses with Compartment ID (CID) filtering, secure and privilege level. It also assigns DMA channels to one or several processors. DMA channels used by Linux should be CID-filtered and statically assigned to CID1 or shared with other CPUs but using semaphore. In case CID filtering is not configured, dma-channel-mask property can be used to specify available DMA channels to the kernel, otherwise such channels will be marked as reserved and can't be used by Linux. STM32 DMA3 is a new STM32 DMA controller, not a new version of an existing one. stm32-dma is not considered for reuse because register layout is completely different and doesn't rely on descriptors mechanism. stm32-mdma is based on descriptors mechanism but there are significant differences in register layout and descriptors structure. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-6-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>