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2017-01-30drm/vc4: Remove vc4_debugfs_cleanup()Noralf Trønnes3-8/+0
drm_debugfs_cleanup() now removes all minor->debugfs_list entries automatically, so the drm_driver.debugfs_cleanup callback is not needed. Cc: eric@anholt.net Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170126225621.12314-17-noralf@tronnes.org
2017-01-28drm: zte: add tvenc driver supportShawn Guo6-0/+446
It adds the TV Encoder driver to support video output in PAL and NTSC format. The driver uses syscon/regmap interface to configure register bit sitting in SYSCTRL module for DAC power control. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28dt: add bindings for ZTE tvenc deviceShawn Guo1-0/+15
It adds bindings doc for ZTE VOU TV Encoder device. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Rob Herring <robh@kernel.org>
2017-01-28drm: zte: add function to configure vou_ctrl dividersShawn Guo3-0/+120
The clock control module (CRM) cannot always provide desired frequency for all VOU output devices. That's why VOU integrates a few dividers to further divide the clocks from CRM. Let's add an interface for configuring these dividers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: move struct vou_inf into zx_vou driverShawn Guo3-33/+35
Although data in struct vou_inf is defined per output device, it doesn't belong to the device itself but VOU control module. All these data can just be defined in VOU driver, and output device driver only needs to invoke VOU driver function with device ID to enable/disable specific output device. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: add interlace mode supportShawn Guo2-2/+65
It adds interlace mode support in VOU TIMING_CTRL and channel control block, so that VOU driver gets ready to support output device in interlace mode like TV Encoder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: add overlay plane supportShawn Guo4-29/+413
It enables VOU VL (Video Layer) to support overlay plane with scaling function. VL0 has some quirks on scaling support. We choose to skip it and only adds VL1 and VL2 into DRM core for now. Function zx_plane_atomic_disable() gets moved around with no changes to save a forward declaration. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: add .atomic_disable hook to disable graphic layerShawn Guo4-20/+69
There are a few hardware bits for each graphic layer to control main/aux channel and clock selection, as well as the layer enabling. These bits sit outside the layer block itself, but in VOU control glue block. We currently set these bits up at CRTC initialization for once, and do not support disabling the layer. This patch creates a pair of functions zx_vou_layer_enable[disable] to be invoked from plane hooks .atomic_update and .atomic_disable to set up and tear down the layer. This is generic for both graphic and video layers, so it will make the overlay plane support to be added later much easier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: make zx_plane accessible from zx_vou driverShawn Guo3-45/+33
Move struct zx_plane from zx_plane.c to zx_plane.h, so that it can be accessed from zx_vou driver, and we can save the use of struct zx_layer_data completely. More importantly, those additional data used by VOU controller to enable/disable graphic and video layers can later be added and accessed much more easily from zx_vou driver. While at it, we make two changes to zx_plane_init() interface: - Encode struct device pointer in zx_plane, so that we do not need to pass it as a parameter. - Change return of zx_plane_init() from struct drm_plane pointer to error code, since we can get the pointer from zx_plane in zx_vou driver now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-01-28drm: zte: support hdmi audio through spdifShawn Guo6-0/+184
It enables HDMI audio support through SPDIF interface based on generic hdmi-audio-codec driver. The HDMI hardware supports more audio interfaces than SPDIF, like I2S, which may be added later. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-01-28drm: zte: select VIDEOMODE_HELPERS in KconfigShawn Guo1-0/+1
ZTE DRM driver uses drm_display_mode_to_videomode() in function zx_crtc_enable(). Select VIDEOMODE_HELPERS in Kconfig to fix the following link error. LD vmlinux.o MODPOST vmlinux.o drivers/built-in.o: In function `zx_crtc_enable': :(.text+0xbdeb8): undefined reference to `drm_display_mode_to_videomode' Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-01-27dma/fence: Export enable-signaling tracepoint for emission by driversChris Wilson1-0/+1
Currently this tracepoint is solely used by dma_fence_enable_sw_signaling, however I have a need to manually perform the hw enabling of the signaling and would like to emit this tracepoint for completeness. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170124115758.31353-1-chris@chris-wilson.co.uk
2017-01-27drm/amdgpu: fix amdgpu_bo_va_mapping flagsChristian König3-3/+3
They are 64bit not 32 for a while now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: access stolen VRAM directly on CZ (v2)Christian König1-1/+8
We don't need to use the PCI BAR on APUs. This allows us to access the full VRAM directly without being limited by the BAR size. v2: squash in 64bit shift fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: access stolen VRAM directly on KV/KB (v2)Christian König1-1/+8
We don't need to use the PCI BAR on APUs. This allows us to access the full VRAM directly without being limited by the BAR size. v2: squash in 64bit shift fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: fix kernel panic when dpm disabled on Kv.Rex Zhu1-0/+3
Return early if it's disabled. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: fix dpm bug on Kv.Rex Zhu1-3/+41
1. current_ps/request_ps not update. 2. compare crrent_ps and request_ps, if same, don't re-set power state. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/powerplay: fix regresstion issue can't set manual dpm mode.Rex Zhu1-0/+3
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: handle vfct with multiple vbios imagesAlex Deucher1-32/+34
The vfct table can contain multiple vbios images if the platform contains multiple GPUs. Noticed by netkas on phoronix forums. This patch fixes those platforms. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2017-01-27drm/radeon: handle vfct with multiple vbios imagesAlex Deucher1-30/+36
The vfct table can contain multiple vbios images if the platform contains multiple GPUs. Noticed by netkas on phoronix forums. This patch fixes those platforms. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2017-01-27drm/amdgpu: move misc si headers into amdgpuAlex Deucher8-6/+6
Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: remove unused header si_reg.hAlex Deucher1-105/+0
All of these are available elsewhere. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/radeon: drop pitcairn dpm quirksAlex Deucher1-46/+1
No longer necessary with the new 58 mc ucode. bug: https://bugs.freedesktop.org/show_bug.cgi?id=76490 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: drop pitcairn dpm quirksAlex Deucher1-46/+1
No longer necessary with the new 58 mc ucode. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm: radeon: radeon_ttm: Handle return NULL error from ioremap_nocacheArvind Yadav1-0/+2
Here, If ioremap_nocache will fail. It will return NULL. Kernel can run into a NULL-pointer dereference. This error check will avoid NULL pointer dereference. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/amdgpu/amdgpu_ttm: Handle return NULL error from ioremap_nocacheArvind Yadav1-0/+2
Here, If ioremap_nocache will fail. It will return NULL. Kernel can run into a NULL-pointer dereference. This error check will avoid NULL pointer dereference. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: add new virtual display IDYintian Tao1-1/+2
In the case of pass-through, amdgpu.ko may be included into a image with the hard code ID therefore loading driver with specified virtual display ID will lose efficacy when the BDF of GPU modifies.So add the new ID string "all" for it as same as vf case what does. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/amdgpu: remove the uncessary parameter for ib schedulerJunwei Zhang13-18/+17
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: Bring bo creation in line with radeon driver (v2)Nils Holland1-0/+20
Add the bo creation changes that have been done to the radeon driver in recent times, e.g. disable GTT WC on 32 bit because it is broken there, and also disable it generally (and print a warning message) when CONFIG_X86_PAT is not set. v2: agd: fix warning in defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) case Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Holland <nholland@tisys.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/powerplay: fix misspelling in header guardNicolas Iooss1-1/+1
In smu7_clockpowergating.h, the #ifndef statement which prevents multiple inclusions of the header file uses _SMU7_CLOCK_POWER_GATING_H_ but the following #define statement uses _SMU7_CLOCK__POWER_GATING_H_. Signed-off-by: Nicolas Iooss <nicolas.iooss_linux@m4x.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/ttm: revert "add optional LRU removal callback v2"Christian König2-14/+5
Without the custom LRU management the callback is not used any more. agd: fix trivial warning Reviewed-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/ttm: revert "implement LRU add callbacks v2"Christian König13-45/+5
The additional housekeeping had too much CPU overhead, let's use the BO priorities instead. agd: also revert hibmc changes Reviewed-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: double the priority of kernel allocationsChristian König1-0/+2
Give kernel allocations a higher priority cause it is often more work to swap them back in. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: user BO priority instead of self coding it (v2)Christian König3-79/+5
Keeping groups of BOs on the LRU is to time consuming on command submission. Instead use the newly added BO priority to give a certain eviction order. v2: agd: trivial warning fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/ttm: add BO priorities for the LRUsChristian König4-27/+52
This way the driver can specify a priority for a BO which has the effect that a BO is only evicted when all other BOs with a lower priority are evicted first. Reviewed-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/ttm: remove allow_errors parameter from ttm_bo_force_list_cleanChristian König1-17/+11
Not allowing errors here is completely pointless and actually dangerous cause trying to continue on an error can cause an endless loop. Reviewed-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu/vi: fix mailbox irq mistakeXiangliang Yu1-3/+3
For virt, freed mailbox irq should be handled in hw fini, not hw init. Correct it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: fix reboot failure issue for virtualizationXiangliang Yu1-0/+6
Reboot process will call HW fini functions of IP blocks. For virt, need to send event three before hw fini and send event four after hw fini. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/amdgpu: Add PCI info to gca_config debugfsTom St Denis1-1/+7
So we can determine which device the entry is before connecting a display. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:insert switch buffer only for VM submitMonk Liu1-1/+1
for non-VM submit which is from kernel side, no need to switch buffer at all. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:Preamble is forbid to be ignored in SRIOVMonk Liu1-1/+2
SR-IOV requires the preamble. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:set cond_exec polling value to 1 in ring_initMonk Liu2-4/+3
no need to set it per ib_schedule(), hw won't override this polling address. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)Monk Liu1-1/+9
to support SRIOV preemption. v2: fix emit_frame_size Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:introduce new flag to identify VM domain for cntx_ctrlMonk Liu2-0/+4
To determine whether the context uses GPUVM or not. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:implement CE/DE meta-init routinesMonk Liu1-0/+61
those package need to insert into ring buffer for SRIOV case. they are used to let CP do preemption. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:implement ring_write_multipleMonk Liu1-0/+31
Write multiple dwords to the ring. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:add META_DATA struct for CSA/SRIOV v2Monk Liu3-0/+120
META-DATA is used in GFX cmd submit, we have two format suit for META-DATA-init, one is legacy and another is for chained-ib preempt, which is used in vulkan UMD. v2: drop use CP version number to judge if chain-ib supports or not, we wait for it mature Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: refine ci uvd dpm code.Rex Zhu1-1/+10
Fix up the powergating logic. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Ack-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: simplify allocation of scratch regsNils Wallménius5-34/+11
The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: Refactor flip into prepare submit and submit. (v3)Andrey Grodzovsky2-28/+123
Make pflip atomic friendly. Split the fuinction into whatever can fail part and the actual flip submit part. Call the pre-submit function before atomic states are swapped so in case of error we can fail the IOCTL. v2: Update due to target_vblank code change. Fix identetation. Change return type for amdgpu_crtc_submit_flip to void v3: agd: fix formatting Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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