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2024-07-15irqchip/imx-irqsteer: Handle runtime power management correctlyShenwei Wang1-3/+21
The power domain is automatically activated from clk_prepare(). However, on certain platforms like i.MX8QM and i.MX8QXP, the power-on handling invokes sleeping functions, which triggers the 'scheduling while atomic' bug in the context switch path during device probing: BUG: scheduling while atomic: kworker/u13:1/48/0x00000002 Call trace: __schedule_bug+0x54/0x6c __schedule+0x7f0/0xa94 schedule+0x5c/0xc4 schedule_preempt_disabled+0x24/0x40 __mutex_lock.constprop.0+0x2c0/0x540 __mutex_lock_slowpath+0x14/0x20 mutex_lock+0x48/0x54 clk_prepare_lock+0x44/0xa0 clk_prepare+0x20/0x44 imx_irqsteer_resume+0x28/0xe0 pm_generic_runtime_resume+0x2c/0x44 __genpd_runtime_resume+0x30/0x80 genpd_runtime_resume+0xc8/0x2c0 __rpm_callback+0x48/0x1d8 rpm_callback+0x6c/0x78 rpm_resume+0x490/0x6b4 __pm_runtime_resume+0x50/0x94 irq_chip_pm_get+0x2c/0xa0 __irq_do_set_handler+0x178/0x24c irq_set_chained_handler_and_data+0x60/0xa4 mxc_gpio_probe+0x160/0x4b0 Cure this by implementing the irq_bus_lock/sync_unlock() interrupt chip callbacks and handle power management in them as they are invoked from non-atomic context. [ tglx: Rewrote change log, added Fixes tag ] Fixes: 0136afa08967 ("irqchip: Add driver for imx-irqsteer controller") Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240703163250.47887-1-shenwei.wang@nxp.com
2024-07-15irqchip/gic-v3: Pass #redistributor-regions to gic_of_setup_kvm_info()Geert Uytterhoeven1-9/+4
The caller of gic_of_setup_kvm_info() already queried DT for the value of the #redistributor-regions property. So just pass this value, instead of doing the DT look-up again in the callee. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/808286a3ac08f60585ae7e2c848e0f9b3cb79cf8.1719912215.git.geert+renesas@glider.be
2024-07-15irqchip/bcm2835: Enable SKIP_SET_WAKE and MASK_ON_SUSPENDStefan Wahren1-1/+3
The BCM2835 ARMCTRL interrupt controller doesn't provide any facility to configure the wakeup sources. That's the reason why the driver lacks the irq_set_wake() callback for the interrupt chip. But this prevent to properly enter power management states like "suspend to idle". Enable the flags IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND so the interrupt suspend logic can handle the chip correctly. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-07-15irqchip/gic-v4: Make sure a VPE is locked when VMAPP is issuedMarc Zyngier1-2/+6
In order to make sure that vpe->col_idx is correctly sampled when a VMAPP command is issued, the vpe_lock must be held for the VPE. This is now possible since the introduction of the per-VM vmapp_lock, which can be taken before vpe_lock in the correct locking order. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nianyao Tang <tangnianyao@huawei.com> Link: https://lore.kernel.org/r/20240705093155.871070-4-maz@kernel.org
2024-07-15irqchip/gic-v4: Substitute vmovp_lock for a per-VM lockMarc Zyngier2-15/+20
vmovp_lock is abused in a number of cases to serialise updates to vlpi_count[] and deal with map/unmap of a VM to ITSs. Instead, provide a per-VM lock and revisit the use of vlpi_count[] so that it is always wrapped in this per-VM vmapp_lock. This reduces the potential contention on a concurrent VMOVP command, and paves the way for subsequent VPE locking that holding vmovp_lock actively prevents due to the lock ordering. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nianyao Tang <tangnianyao@huawei.com> Link: https://lore.kernel.org/r/20240705093155.871070-3-maz@kernel.org
2024-07-15irqchip/gic-v4: Always configure affinity on VPE activationMarc Zyngier1-9/+4
There are currently two paths to set the initial affinity of a VPE: - at activation time on GICv4 without the stupid VMOVP list, and on GICv4.1 - at map time for GICv4 with VMOVP list The latter location may end-up modifying the affinity of VPE that is currently running, making the results unpredictible. Instead, unify the two paths, making sure to set the initial affinity only at activation time. Reported-by: Nianyao Tang <tangnianyao@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nianyao Tang <tangnianyao@huawei.com> Link: https://lore.kernel.org/r/20240705093155.871070-2-maz@kernel.org
2024-06-25Revert "irqchip/dw-apb-ictl: Support building as module"Thomas Gleixner2-11/+4
This reverts commit 7cc4f309c933ec5d64eea31066fe86bbf9e48819. Causes build fails. Reported-by: Mark Brown <broonie@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jisheng Zhang <jszhang@kernel.org> https://lore.kernel.org/oe-kbuild-all/202406250214.WZEjWnnU-lkp@intel.com/
2024-06-25Revert "Loongarch: Support loongarch avec"Thomas Gleixner14-517/+10
This reverts commit 760d7e719499d64beea62bfcf53938fb233bb6e7. This results in build failures and has other issues according to Tianyang. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Tianyang Zhang <zhangtianyang@loongson.cn> Closes: https://lore.kernel.org/oe-kbuild-all/202406240451.ygBFNyJ3-lkp@intel.com/
2024-06-24arm64: Kconfig: Allow build irq-stm32mp-exti driver as moduleAntonio Borneo1-1/+0
Drop auto-selecting the driver, so it can be built either as a module or built-in. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-9-antonio.borneo@foss.st.com
2024-06-24ARM: stm32: Allow build irq-stm32mp-exti driver as moduleAntonio Borneo1-1/+0
Drop auto-selecting the driver, so it can be built either as a module or built-in. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-8-antonio.borneo@foss.st.com
2024-06-24irqchip/stm32mp-exti: Allow building as moduleAntonio Borneo2-13/+10
Allow to build the driver as a module by adding the necessarily hooks in Kconfig and in the driver's code. Since all the probe dependencies linked to this driver have already been fixed, remove the not longer relevant 'arch_initcall'. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-7-antonio.borneo@foss.st.com
2024-06-23irqchip/stm32mp-exti: Rename internal symbolsAntonio Borneo1-160/+152
Rename all the internal symbols accordingly to the new name of the driver. Renaming done automatically through sed rules: s/stm32_exti_set_type/stm32mp_exti_convert_type/g s/stm32_exti_h_/stm32mp_exti_/g s/stm32_exti/stm32mp_exti/g s/stm32_bank/bank/g s/stm32_/stm32mp_/g s/STM32_/STM32MP_/g s/STM32MP1_/STM32MP_/g s/stm32mp1_exti_/stm32mp_exti_/g s/stm32-exti-h/stm32mp-exti/g Manually fix some indentation after the rename. [ tglx: Mop up more coding style issues while at it ] Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-6-antonio.borneo@foss.st.com
2024-06-23irqchip/stm32-exti: Split MCU and MPU codeAntonio Borneo4-667/+751
Keep only the code for ARMv7m STM32 MCUs in in stm32-exti.c and split out the code for ARMv7a & ARMv8a STM32MPxxx MPUs into stm32mp-exti.c Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-5-antonio.borneo@foss.st.com
2024-06-23arm64: Kconfig: Select STM32MP_EXTI on STM32 platformsAntonio Borneo1-1/+1
Use the new config flag to build the correct driver that will be extracted from the old code. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-4-antonio.borneo@foss.st.com
2024-06-23ARM: stm32: Use different EXTI driver on ARMv7m and ARMv7aAntonio Borneo1-1/+2
Build the proper driver by selecting the appropriate config flag. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-3-antonio.borneo@foss.st.com
2024-06-23irqchip/stm32-exti: Add CONFIG_STM32MP_EXTIAntonio Borneo1-0/+4
To guarantee bisect-ability during the split of stm32-exti in MCU and MPU code, introduce CONFIG_STM32MP_EXTI. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240620083115.204362-2-antonio.borneo@foss.st.com
2024-06-23irqchip/dw-apb-ictl: Support building as moduleJisheng Zhang2-4/+11
The driver is now always built in. In some synaptics ARM64 SoCs it is used as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. Enable it to be built as a module and handle built-in usage correctly, so that it continues working on systems where it is the main interrupt controller. [ tglx: Massage changelog ] Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614153449.2083-1-jszhang@kernel.org
2024-06-23irqchip/riscv-aplic: Simplify the initialization codeJinjie Ruan1-7/+6
The initialization code has an is_of_node() check and invokes to_of_node() for every of_property_*() invocation. to_of_node() has a is_of_node() check already, so simplify the code by invoking to_of_node() and checking that for NULL. If not NULL hand in the node pointer to of_property_*(). The same applies to of_property_*() which fails when invoked with a NULL node pointer. [ tglx: Massaged change log ] Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20240603125652.791601-1-ruanjinjie@huawei.com
2024-06-23Loongarch: Support loongarch avecTianyang Zhang14-10/+517
Introduce the advanced extended interrupt controllers. This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. [ tglx: Fixed up coding style. Made on/offline functions void ] Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Co-developed-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240604125026.18745-1-zhangtianyang@loongson.cn
2024-06-23irqchip/armada-370-xp: Add support for 32 MSI interrupts on non-IPI platformsPali Rohár1-14/+63
The doorbell interrupts have the following layout on IPI vs no-IPI platforms: | 0...7 | 8...15 | 16...31 | ------------------+---------+----------+---------------------+ IPI platform | IPI | n/a | MSI | ------------------+---------+----------+---------------------+ non-IPI platform | MSI | ------------------+------------------------------------------+ Currently the driver only allows for the upper 16...31 interrupts for MSI domain (i.e. the MSI domain has only 16 interrupts). On platforms where IPI is not available, we can use whole 32 MSI interrupts. Implement support also for the lower 16 MSI interrupts on non-IPI platforms. [ Marek: refactored, changed commit message ] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
2024-06-23irqchip/armada-370-xp: Do not touch IPI registers on platforms without IPIPali Rohár1-2/+10
On platforms where IPI is not available in the MPIC, the IPI registers instead represent an additional set of MSI interrupt registers (currently unused by the driver). Do not touch these registers on platforms where IPI is not available in the MPIC. [ Marek: refactored, changed commit message ] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
2024-06-23irqchip/armada-370-xp: Only call ipi_resume() if IPI is availablePali Rohár1-2/+16
IPI is available only on systems where the mpic controller does not have a parent interrupt defined (e.g. on Armada XP). If a parent interrupt is defined, inter-processor interrupts are handled by an interrupt controller higher in the hierarchy (most probably a parent GIC). Only call ipi_resume() on systems where IPI is available in the mpic controller. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> [ refactored a little and changed commit message ]
2024-06-23irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1Pali Rohár1-0/+4
IRQs 0 (IPI) and 1 (MSI) are handled internally by this driver, generic_handle_domain_irq() is never called for these IRQs. Disallow mapping these IRQs. [ Marek: changed commit message ] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
2024-06-23irqchip/armada-370-xp: Use atomic_io_modify() instead of another spinlockMarek Behún1-9/+3
Use the dedicated atomic_io_modify() instead of a open coded spin_lock() + readl() + writel() + spin_unlock() sequence. This allows to drop the irq_controller_lock spinlock from the driver. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
2024-06-23irqchip: Add missing MODULE_DESCRIPTION() macrosJeff Johnson3-0/+3
On x86, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/irqchip/irq-ts4800.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/irqchip/irq-meson-gpio.o Add the missing invocation of the MODULE_DESCRIPTION() macro to all files which have a MODULE_LICENSE(). This includes a 3rd file, irq-mvebu-pic.c, which did not produce a warning with the x86 allmodconfig, but which may cause this warning with other kernel configurations. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240608-md-drivers-irqchip-v1-1-dd02c3229277@quicinc.com
2024-06-23irqchip/renesas-rzg2l: Reorder function calls in rzg2l_irqc_irq_disable()Lad Prabhakar1-1/+1
The order of function calls in the disable operation should be the reverse of that in the enable operation. Thus, reorder the function calls to first disable the parent IRQ chip before disabling the TINT IRQ. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Link: https://lore.kernel.org/r/20240606194813.676823-1-prabhakar.mahadev-lad.rj@bp.renesas.com
2024-06-21irqchip/riscv-intc: Remove asmlinkageJisheng Zhang1-2/+2
The two functions riscv_intc_aia_irq() and riscv_intc_irq() are only called by C functions. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240614151955.1949-1-jszhang@kernel.org
2024-06-17irqdomain: Make build work for CONFIG_GENERIC_IRQ_CHIP=nThomas Gleixner1-0/+10
ld: kernel/irq/irqdomain.o: in function `irq_domain_instantiate': kernel/irq/irqdomain.c:296:(.text+0x10dd): undefined reference to `irq_domain_alloc_generic_chips' ld: kernel/irq/irqdomain.c:313:(.text+0x1218): undefined reference to `irq_domain_remove_generic_chips' ld: kernel/irq/irqdomain.o: in function `irq_domain_remove': kernel/irq/irqdomain.c:349:(.text+0x1ddf): undefined reference to `irq_domain_remove_generic_chips' Provide the required stubs. Fixes: e6f67ce32e8e ("irqdomain: Add support for generic irq chips creation before publishing a domain") Reported-by: Borislav Betkov <bp@alien8.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2024-06-17MAINTAINERS: Add the Microchip LAN966x OIC driver entryHerve Codina1-0/+6
After contributing the driver, add myself as the maintainer for the Microchip LAN966x OIC driver. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-24-herve.codina@bootlin.com
2024-06-17irqchip: Add support for LAN966x OICHerve Codina3-0/+291
The Microchip LAN966x outband interrupt controller (OIC) maps the internal interrupt sources of the LAN966x device to an external interrupt. When the LAN966x device is used as a PCI device, the external interrupt is routed to the PCI interrupt. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-23-herve.codina@bootlin.com