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2015-03-17drm/i915: Rewrite some some of the FDI lane checksVille Syrjälä1-8/+7
2015-03-17drm/i915/skl: Enable the RPS interrupts programmingAkash Goel1-14/+3
2015-03-17drm/i915/skl: Enabling processing of Turbo interruptsAkash Goel1-5/+0
2015-03-17drm/i915/skl: Updated the i915_frequency_info debugfs functionAkash Goel1-8/+17
2015-03-17drm/i915: Simplify the way BC bifurcation state consistency is keptAnder Conselvan de Oliveira1-36/+10
2015-03-17drm/i915/skl: Updated the act_freq_mhz_show sysfs functionAkash Goel1-1/+3
2015-03-17drm/i915/skl: Updated the gen9_enable_rps functionAkash Goel1-15/+13
2015-03-17drm/i915/skl: Updated the gen6_rps_limits functionAkash Goel1-5/+11
2015-03-17drm/i915/skl: Restructured the gen6_set_rps_thresholds functionAkash Goel1-36/+32
2015-03-17drm/i915/skl: Updated the gen6_set_rps functionAkash Goel1-1/+4
2015-03-17drm/i915/skl: Updated the gen6_init_rps_frequencies functionAkash Goel1-0/+7
2015-03-17drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()Akash Goel1-2/+6
2015-03-17drm/i915/skl: Added new macrosAkash Goel2-0/+10
2015-03-17drm/i915: remove indirection in the PCI ID macrosJani Nikula1-24/+25
2015-03-17drm/i915: Use FW_WM() macro for older gmch platforms tooVille Syrjälä2-22/+24
2015-03-17drm/i915: Add polish to VLV WM shift+mask operationsVille Syrjälä2-38/+46
2015-03-17drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()Ville Syrjälä1-2/+2
2015-03-17drm/i915: Reduce clutter by using the local plane pointerVille Syrjälä1-1/+1
2015-03-17drm/i915: Remove debug prints from primary plane update funcsVille Syrjälä1-11/+0
2015-03-17drm/i915: Add ULL postfix to VGT_MAGIC constantDaniel Vetter1-1/+1
2015-03-17drm/fourcc: 64 #defines need ULL postfixDaniel Vetter1-1/+1
2015-03-17drm/i915: Don't assume primary & cursor are always on for wm calculation (v4)Matt Roper1-23/+39
2015-03-17drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flipsChris Wilson1-8/+9
2015-03-17drm/i915: Disable DDR DVFS on CHVVille Syrjälä2-0/+39
2015-03-17drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä2-0/+21
2015-03-17drm/i915: Program PFI credits for VLVVidya Srinivas2-0/+46
2015-03-17drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä3-142/+173
2015-03-17drm/i915: Make sure we invalidate frontbuffer on fbcon.Rodrigo Vivi1-1/+26
2015-03-17drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman2-12/+33
2015-03-17drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman2-0/+10
2015-03-17drm/i915: Disable M2 frac division for integer caseVijay Purushothaman2-4/+11
2015-03-17drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven1-3/+3
2015-03-17drm/i915: Use crtc->state->active in ilk/skl watermark calculations (v3)Matt Roper1-8/+8
2015-03-17drm/i915: Update intel_crtc_active() to use state values (v2)Matt Roper1-1/+5
2015-03-17drm/i915: Exit early from psr_status if PSR is not supported by the deviceDamien Lespiau1-12/+15
2015-03-17drm/i915: Fix chv cdclk supportVille Syrjälä1-16/+7
2015-03-17drm/i915: Allow pixel clock up to 95% of cdclk on CHVVille Syrjälä1-5/+7
2015-03-17drm/i915/skl: port A fuse straps don't work on early SKL steppingsJesse Barnes1-3/+8
2015-03-17drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau1-1/+3
2015-03-17drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau1-1/+1
2015-03-17drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau2-0/+35
2015-03-17drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau1-1/+1
2015-03-17drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau1-4/+6
2015-03-17drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau3-7/+14
2015-03-17drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee2-2/+40
2015-03-17drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee2-6/+36
2015-03-17drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä2-6/+16
2015-03-17drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä2-1/+59
2015-03-17drm/i915: Pass plane to vlv_compute_drain_latency()Ville Syrjälä1-26/+16
2015-03-17drm/i915: Reorganize VLV DDL setupVille Syrjälä2-15/+40
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