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2019-11-13clk: tegra: Use match_string() helper to simplify the codeYueHaibing1-8/+4
match_string() returns the array index of a matching string. Use it instead of the open-coded implementation. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191109034226.21044-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-13clk: pxa: fix one of the pxa RTC clocksRobert Jarzmik1-0/+1
The pxa27x platforms have a single IP with 2 drivers, sa1100-rtc and rtc-pxa drivers. A previous patch fixed the sa1100-rtc case, but the pxa-rtc wasn't fixed. This patch completes the previous one. Fixes: 8b6d10345e16 ("clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Link: https://lkml.kernel.org/r/20191026194420.11918-1-robert.jarzmik@free.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-13clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()Baolin Wang1-1/+1
The syscon_regmap_lookup_by_phandle() will never return NULL, thus use IS_ERR() to validate the return value instead of IS_ERR_OR_NULL(). Fixes: d41f59fd92f2 ("clk: sprd: Add common infrastructure") Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lkml.kernel.org/r/1995139bee5248ff3e9d46dc715968f212cfc4cc.1570520268.git.baolin.wang@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-13clk: armada-xp: remove unused codeYueHaibing1-26/+0
drivers/clk/mvebu/armada-xp.c:171:38: warning: mv98dx3236_coreclks defined but not used [-Wunused-const-variable=] drivers/clk/mvebu/armada-xp.c:213:41: warning: mv98dx3236_gating_desc defined but not used [-Wunused-const-variable=] They are not used since commit 337072604224 ("clk: mvebu: Expand mv98dx3236-core-clock support"). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191111140420.36092-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-11clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing1-0/+2
If CONFIG_PM_SLEEP is n, build fails: drivers/clk/tegra/clk-tegra210.c:3426:13: error: tegra210_clk_suspend undeclared here (not in a function); did you mean tegra_clk_ndspeed? .suspend = tegra210_clk_suspend, ^~~~~~~~~~~~~~~~~~~~ tegra_clk_ndspeed drivers/clk/tegra/clk-tegra210.c:3427:12: error: tegra210_clk_resume undeclared here (not in a function); did you mean tegra210_clk_suspend? .resume = tegra210_clk_resume, Use ifdef to guard this. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 27d10d548c04 ("clk: tegra: Add suspend and resume support on Tegra210") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEPDmitry Osipenko1-0/+13
The new CPUIDLE driver uses the Tegra's CLK API and that driver won't strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2-18/+32
There is no need to re-configure PLLX if its configuration in unchanged on return from suspend / cpuidle, this saves 300us if PLLX is already enabled (common case for cpuidle). Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni3-4/+163
All the CAR controller settings are lost on suspend when core power goes off. This implement saving and restoring context for all PLLs and clocks during system suspend and resume to have the clocks back to same state for normal operation. Clock driver suspend and resume are registered as syscore_ops as clocks restore need to happen before the other drivers resume to have all their clocks back to the same state as before suspend. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2-45/+45
Move CLK_OUT_ENB and RST_DEVICES registers to clk.h to share these with Tegra clock driver. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni1-4/+4
This patch uses fence_udelay rather than udelay during PLLU initialization to ensure writes to clock registers happens before waiting for specified delay. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni3-0/+59
This patch implements DFLL suspend and resume operation. During system suspend entry, CPU clock will switch CPU to safe clock source of PLLP and disables DFLL clock output. DFLL driver suspend confirms DFLL disable state and errors out on being active. DFLL is re-initialized during the DFLL driver resume as it goes through complete reset during suspend entry. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni1-0/+27
This patch implements restore_context for clk_super_mux and clk_super. During system supend, core power goes off the and context of Tegra CAR registers is lost. So on system resume, context of super clock registers are restored to have them in same state as before suspend. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni4-1/+39
This patch has a fix to enable PLLP branches to CPU before changing the CPU cluster clock source to PLLP for Gen5 Super clock and disables PLLP branches to CPU when not in use. During system suspend entry and exit, CPU source will be switched to PLLP and this needs PLLP branches to be enabled to CPU prior to the switch. On system resume, warmboot code enables PLLP branches to CPU and powers up the CPU with PLLP clock source. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: periph: Add restore_context supportSowjanya Komatineni2-0/+37
This patch implements restore_context support for clk-periph and clk-sdmmc-mux clock operations to restore clock parent and rates on system resume. During system suspend, core power goes off and looses the context of the Tegra clock controller registers. So on system resume, clocks parent and rate are restored back to the context before suspend based on cached data. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2-0/+16
This patch adds support for saving OSC clock frequency and the drive-strength during OSC clock init and creates an API to restore OSC control register value from the saved context. This API is invoked by Tegra210 clock driver during system resume to restore the OSC clock settings. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni1-32/+54
This patch implements save and restore of PLL context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during resume, pll context is restored based on cached rate and state. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni1-0/+9
This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni1-0/+11
This patch implements context restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So on resume, clock dividers are restored back for normal operation. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding2-19/+58
In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and later. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding1-9/+13
In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and later. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding3-8/+8
This makes Tegra124 and Tegra210 consistent with subsequent Tegra generations. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2-8/+49
The SOR0 clock on Tegra210 is very different from the SOR0 clock found on Tegra124. Move the Tegra124 implementation to the Tegra124 driver so that a custom implementation can be provided on Tegra210 without clashing with the existing clock. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding3-3/+2
Later SoC generations implement this clock as SOR1_OUT. For consistency, the Tegra210 implementation was adapted to match the same name in commit 4d1dc4018573 ("dt-bindings: clock: tegra: Add sor1_out clock"). Clean up the remaining pieces by adopting the new name for the internal identifiers and remove the old alias. Note that since both SOR1_SRC and SOR1_OUT were referring to the same device tree clock ID, this does not break device tree ABI. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko6-52/+350
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up. The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: Add API to get index of the clock parentSowjanya Komatineni2-0/+19
This patch adds a new clk_hw_get_parent_index() function that can be used to retrieve the index of a given clock's parent. This can be useful for restoring a clock on system resume. Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-08clk: clk-gpio: propagate rate change to parentMichael Hennerich1-1/+1
For an external clock source, which is gated via a GPIO, the rate change should typically be propagated to the parent clock. The situation where we are requiring this propagation, is when an external clock is connected to override an internal clock (which typically has a fixed rate). The external clock can have a different rate than the internal one, and may also be variable, thus requiring the rate propagation. This rate change wasn't propagated until now, and it's unclear about cases where this shouldn't be propagated. Thus, it's unclear whether this is fixing a bug, or extending the current driver behavior. Also, it's unsure about whether this may break any existing setups; in the case that it does, a device-tree property may be added to disable this flag. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lkml.kernel.org/r/20191108071718.17985-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08clk: qcom: rpmh: Reuse sdm845 clks for sm8150Stephen Boyd1-20/+14
The SM8150 list of clks is almost the same as the list for SDM845, except there isn't an IPA clk. Just point to the SDM845 clks from the SM8150 list for now so we can reduce the amount of struct bloat in this driver. Suggested-by: Vinod Koul <vkoul@kernel.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191107214018.184105-1-sboyd@kernel.org Reviewed-by: Vinod Koul <vkoul@kernel.org>
2019-11-08clk/ti/adpll: allocate room for terminating nullStephen Kitt1-9/+2
The buffer allocated in ti_adpll_clk_get_name doesn't account for the terminating null. This patch switches to devm_kasprintf to avoid overflowing. Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20191019140634.15596-1-steve@sk2.org Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08clk: ast2600: Add RMII RCLK gates for all four MACsAndrew Jeffery1-1/+46
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt7-14/+9
There are a few manually-calculated variable-length struct allocations left, this converts them to use struct_size. Found with the following git grep command git grep -A1 'kzalloc.*sizeof[^_].*+' Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> [sboyd@kernel.org: Add grep command] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driverJeffrey Hugo3-0/+348
The GPUCC manages the clocks for the Adreno GPU found on MSM8998. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185733.15553-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo2-0/+5
Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just some constant ratio from the input across the entire frequency range. It would be great if we could specify the frequency table as a single entry constant ratio instead of a long list, ie: { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, { } So, lets support that. We need to fix a corner case in qcom_find_freq() where if the freq table is non-null, but has no frequencies, we end up returning an "entry" before the table array, which is bad. Then, we need ignore the freq from the table, and instead base everything on the requested freq. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: smd: Add missing pnoc clockJeffrey Hugo1-0/+3
When MSM8998 support was added, and analysis was done to determine what clocks would be consumed. That analysis had a flaw, which caused the pnoc to be skipped. The pnoc clock needs to be on to access the uart for the console. The clock is on from boot, but has no consumer votes in the RPM. When we attempt to boot the modem, it causes the RPM to turn off pnoc, which kills our access to the console and causes CPU hangs. We need pnoc to be defined, so that clk_smd_rpm_handoff() will put in an implicit vote for linux and prevent issues when booting modem. Hopefully pnoc can be consumed by the interconnect framework in future so that Linux can rely on explicit votes. Fixes: 6131dc81211c ("clk: qcom: smd: Add support for MSM8998 rpm clocks") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191107190615.5656-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Enumerate clocks and reset needed to boot the 8998 modemJeffrey Hugo2-0/+78
We need to control five additional clocks and a reset inorder to boot the modem on msm8998. If we can boot the modem, we have a place to run the wlan firmware and get wifi up and running. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191107192136.5880-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180Taniya Das1-0/+19
Add support for clock RPMh driver to vote for ARC and VRM managed clock resources. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1572371299-16774-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07dt-bindings: clock: Introduce RPMHCC bindings for SC7180Taniya Das1-0/+1
Add compatible for SC7180 RPMHCC. Signed-off-by: Taniya Das <tdas@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1572371299-16774-3-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Sort compatible list] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock bindingsTaniya Das2-27/+48
The RPMHCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1572371299-16774-2-git-send-email-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Add Global Clock controller (GCC) driver for SC7180Taniya Das3-0/+2460
Add support for the global clock controller found on SC7180 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-6-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07dt-bindings: clock: Add sc7180 GCC clock bindingTaniya Das2-0/+169
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-5-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Reword subject to make sc7180 specific, sort compatible] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindingsTaniya Das2-94/+174
The GCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-4-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: common: Return NULL from clk_hw OF providerTaniya Das1-1/+1
Return NULL in the cases where the clk_hw is not registered with the clock provider, but the clock consumer still requests for a clock id. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-3-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: rcg: update the DFS macro for RCGTaniya Das2-49/+49
Update the init data name for each of the dynamic frequency switch controlled clock associated with the RCG clock name, so that it can be generated as per the hardware plan. Thus update the macro accordingly. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: remove unneeded semicolonYueHaibing1-2/+2
remove unneeded semicolon. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191025093332.27592-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Add Q6SSTOP clock controller for QCS404Govind Singh4-0/+250
Add support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP. Signed-off-by: Govind Singh <govinds@codeaurora.org> Link: https://lkml.kernel.org/r/20191011132928.9388-3-govinds@codeaurora.org [sboyd@kernel.org: Sort makefile] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-05clk: rockchip: protect the pclk_usb_grf as critical on px30Heiko Stuebner1-1/+2
Make this clock a real critical clock, so that writes to the usbphy grf always succeed. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-5-heiko@sntech.de
2019-11-05clk: rockchip: add video-related niu clocks as critical on px30Heiko Stuebner1-5/+10
Video-In and -Out interconnect clocks need to stay on all the time for the peripheral to work and we do not model the actual interconnect at this point. So mark them as critical for now. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-4-heiko@sntech.de
2019-11-05clk: rockchip: move px30 critical clocks to correct clock controllerHeiko Stuebner1-4/+4
The clocks in the px30 critical clock section are from the regular cru not the pmucru, so move them to the correct place. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-3-heiko@sntech.de
2019-11-05clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandcFinley Xiao1-4/+40
Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50% duty cycle, divfree50 can generate clock of 50% duty cycle even in odd value divisor. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917081903.25139-2-heiko@sntech.de
2019-11-05clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandcFinley Xiao1-0/+2
EMMC and SDIO already have these clock-ids (still unused) only sdmmc is missing them, so fix that. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917081903.25139-1-heiko@sntech.de
2019-11-05clk: sunxi-ng: h3: Export MBUS clockJernej Skrabec2-5/+1
MBUS clock will be referenced in MBUS controller node. Export it. Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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