From 070d546258257c75c65a2f15da558eb96bce550c Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 7 Apr 2025 11:56:06 -0500 Subject: dt-bindings: phy: rockchip: Add missing "phy-supply" property Several Rockchip PHYs use the "phy-supply" property, but don't document it. Add it to the current known users. Signed-off-by: Rob Herring (Arm) Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250407165607.2937088-1-robh@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 3 +++ Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml | 3 +++ Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 3 +++ 3 files changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 888e6b2aac5a..3e101c3c5ea9 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -42,6 +42,9 @@ properties: - const: phy - const: apb + phy-supply: + description: Single PHY regulator + rockchip,enable-ssc: type: boolean description: diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml index b42f1272903d..8b7059d5b182 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml @@ -47,6 +47,9 @@ properties: - const: pcs_apb - const: pma_apb + phy-supply: + description: Single PHY regulator + rockchip,dp-lane-mux: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index ba67dca5a446..d7de8b527c5c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -46,6 +46,9 @@ properties: reset-names: const: phy + phy-supply: + description: Single PHY regulator + rockchip,phy-grf: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the syscon managing the phy "general register files" -- cgit v1.2.3-59-g8ed1b From 23f793850e9ee7390584c0809f085d6c88de7d3f Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Thu, 10 Apr 2025 14:01:13 +0530 Subject: dt-bindings: phy: samsung,usb3-drd-phy: add exynos7870-usbdrd-phy compatible Add the compatible string "samsung,exynos7870-usbdrd-phy" to the documentation. The devicetree node requires two clocks, named "phy" and "ref" (same as clocks required by Exynos5). Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250410-exynos7870-usbphy-v2-2-2eb005987455@disroot.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 27295acbba76..fdddddc7d611 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -30,6 +30,7 @@ properties: - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy - samsung,exynos7-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy clocks: @@ -184,6 +185,7 @@ allOf: enum: - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy then: properties: -- cgit v1.2.3-59-g8ed1b From 0fbceff4f873500f0d0e632ee2d1e84e9a67b1b4 Mon Sep 17 00:00:00 2001 From: Justin Chen Date: Wed, 2 Apr 2025 11:51:58 -0700 Subject: dt-bindings: phy: brcmstb-usb-phy: Add support for bcm74110 bcm74110 brcmstb usb phy adds further power savings during suspend states. Signed-off-by: Justin Chen Reviewed-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250402185159.2976920-2-justin.chen@broadcom.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml index 580fbe37b37f..843d04027c30 100644 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml @@ -18,6 +18,7 @@ properties: - brcm,bcm4908-usb-phy - brcm,bcm7211-usb-phy - brcm,bcm7216-usb-phy + - brcm,bcm74110-usb-phy - brcm,brcmstb-usb-phy reg: @@ -139,7 +140,9 @@ allOf: properties: compatible: contains: - const: brcm,bcm7216-usb-phy + enum: + - brcm,bcm7216-usb-phy + - brcm,bcm74110-usb-phy then: properties: reg: -- cgit v1.2.3-59-g8ed1b From aae29082b6620c664e97a1e2f2062abc6a58659d Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Wed, 26 Mar 2025 12:10:55 +0400 Subject: dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible The IPQ5018 SoC contains a Gen2 1 and 2-lane PCIe UNIPHY which is the same as the one found in IPQ5332. As such, add IPQ5018 compatible. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-1-e1828fef06c9@outlook.com Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 49 ++++++++++++++++++---- 1 file changed, 41 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml index e39168d55d23..6e9df81441e9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -11,26 +11,24 @@ maintainers: - Varadarajan Narayanan description: - PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs properties: compatible: enum: + - qcom,ipq5018-uniphy-pcie-phy - qcom,ipq5332-uniphy-pcie-phy reg: maxItems: 1 clocks: - items: - - description: pcie pipe clock - - description: pcie ahb clock + minItems: 1 + maxItems: 2 resets: - items: - - description: phy reset - - description: ahb reset - - description: cfg reset + minItems: 2 + maxItems: 3 "#phy-cells": const: 0 @@ -53,6 +51,41 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + resets: + items: + - description: phy reset + - description: cfg reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + examples: - | #include -- cgit v1.2.3-59-g8ed1b From 117d09e2830d6ff6c1bb2dc5629f972504fde51e Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 22 Apr 2025 15:24:26 +0200 Subject: dt-bindings: phy: mtk-xs-phy: Add mt7988 compatible Add compatible for xs-phy on mt7988. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml index a9e3139fd421..3b5253659e6f 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml @@ -49,6 +49,7 @@ properties: - enum: - mediatek,mt3611-xsphy - mediatek,mt3612-xsphy + - mediatek,mt7988-xsphy - const: mediatek,xsphy reg: -- cgit v1.2.3-59-g8ed1b From b484b25a486962b568ada1f55c1b96dfd96b912d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 22 Apr 2025 15:24:27 +0200 Subject: dt-bindings: phy: mtk-xs-phy: support type switch by pericfg Add support for type switch by pericfg register between USB3/PCIe. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml index 3b5253659e6f..0bed847bb4ad 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml @@ -151,6 +151,21 @@ patternProperties: minimum: 1 maximum: 31 + mediatek,syscon-type: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle to syscon used to access the register of type switch, + the field should always be 3 cells long. + items: + - items: + - description: + Phandle to phy type configuration system controller + - description: + Phy type configuration register offset + - description: + Index of config segment + enum: [0, 1, 2, 3] + required: - reg - clocks -- cgit v1.2.3-59-g8ed1b From e00c9aea31035f46b04a13effaa801f8b3419d2a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 11 Apr 2025 11:27:43 +0530 Subject: dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMII The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value of "12" while the existing maximum allowed PHY TYPE is "9", switch back to using "enum" property in the bindings to account for this discontinuity. Signed-off-by: Siddharth Vadapalli Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 15dc8efe6ffe..9af39b33646a 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -99,8 +99,7 @@ patternProperties: Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 9 + enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 12] cdns,num-lanes: description: -- cgit v1.2.3-59-g8ed1b From 2063eedf3c9c4449fbf417c9b84ecd08251c3b34 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 16 Apr 2025 15:24:17 -0500 Subject: dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schema Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the missing "power-domains" property and "port" and "orientation-switch" properties in the child nodes. Omit the previously deprecated properties as they aren't used anywhere. Drop the 2nd example which was pretty much identical to the 1st example. Signed-off-by: Rob Herring (Arm) Acked-by: Greg Kroah-Hartman Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/phy-rockchip-typec.txt | 84 --------------- .../bindings/phy/rockchip,rk3399-typec-phy.yaml | 116 +++++++++++++++++++++ .../devicetree/bindings/usb/rockchip,dwc3.yaml | 2 +- 3 files changed, 117 insertions(+), 85 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt deleted file mode 100644 index 960da7fcaa9e..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ /dev/null @@ -1,84 +0,0 @@ -* ROCKCHIP type-c PHY ---------------------- - -Required properties: - - compatible : must be "rockchip,rk3399-typec-phy" - - reg: Address and length of the usb phy control register set - - rockchip,grf : phandle to the syscon managing the "general - register files" - - clocks : phandle + clock specifier for the phy clocks - - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref"; - - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or - <&cru SCLK_UPHY1_TCPDCORE>; - - assigned-clock-rates : the phy core clk frequency, shall be: 50000000 - - resets : a list of phandle + reset specifier pairs - - reset-names : string reset name, must be: - "uphy", "uphy-pipe", "uphy-tcphy" - -Optional properties: - - extcon : extcon specifier for the Power Delivery - -Required nodes : a sub-node is required for each port the phy provides. - The sub-node name is used to identify dp or usb3 port, - and shall be the following entries: - * "dp-port" : the name of DP port. - * "usb3-port" : the name of USB3 port. - -Required properties (port (child) node): -- #phy-cells : must be 0, See ./phy-bindings.txt for details. - -Deprecated properties, do not use in new device tree sources, these -properties are determined by the compatible value: - - rockchip,typec-conn-dir - - rockchip,usb3tousb2-en - - rockchip,external-psm - - rockchip,pipe-status - -Example: - tcphy0: phy@ff7c0000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb0>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY0>, - <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy0_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy0_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - tcphy1: phy@ff800000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb1>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY1>, - <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy1_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy1_usb3: usb3-port { - #phy-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml new file mode 100644 index 000000000000..91c011f68cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Type-C PHY + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: rockchip,rk3399-typec-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: tcpdcore + - const: tcpdphy-ref + + extcon: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: uphy + - const: uphy-pipe + - const: uphy-tcphy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF). + + dp-port: + type: object + additionalProperties: false + + properties: + '#phy-cells': + const: 0 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to USB Type-C connector + + required: + - '#phy-cells' + + usb3-port: + type: object + additionalProperties: false + + properties: + '#phy-cells': + const: 0 + + orientation-switch: true + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to USB Type-C connector SS port + + required: + - '#phy-cells' + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - dp-port + - usb3-port + +additionalProperties: false + +examples: + - | + #include + + phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0xff7c0000 0x40000>; + rockchip,grf = <&grf>; + extcon = <&fusb0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + + dp-port { + #phy-cells = <0>; + }; + + usb3-port { + #phy-cells = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index fba2cb05ecba..fd1b13c0ed6b 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -18,7 +18,7 @@ description: Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml Type-C PHY - Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt + Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml select: properties: -- cgit v1.2.3-59-g8ed1b From fe750a871d90e081c52ce1988e1fbc85576152a3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 16 Apr 2025 14:02:19 +0200 Subject: dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893 Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI PHY found in this chip is fully compatible with the one found in the MT8183 SoC. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index f6e494d0d89b..acdbce937b0a 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -30,6 +30,7 @@ properties: - const: mediatek,mt8173-mipi-tx - items: - enum: + - mediatek,mt6893-mipi-tx - mediatek,mt8188-mipi-tx - mediatek,mt8195-mipi-tx - mediatek,mt8365-mipi-tx -- cgit v1.2.3-59-g8ed1b From 1b1e949924fb59e98d9401681b139e92e75686ac Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 16 Apr 2025 14:02:20 +0200 Subject: dt-bindings: phy: mediatek,tphy: Add support for MT6893 Add a compatible string for the MediaTek Dimensity 1200 (MT6893) SoC: this chip integrates a MediaTek generic T-PHY version 2. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 6be3aa4557e5..b2218c151939 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -78,6 +78,7 @@ properties: - items: - enum: - mediatek,mt2712-tphy + - mediatek,mt6893-tphy - mediatek,mt7629-tphy - mediatek,mt7986-tphy - mediatek,mt8183-tphy -- cgit v1.2.3-59-g8ed1b From 5b3a91b207c00a8d27f75ce8aaa9860844da72c8 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 30 Apr 2025 17:44:59 +0800 Subject: dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in register PHY_CTRL3 bit[31:29]. 011: Corresponds to a launch amplitude of 1.12 V. 010: Corresponds to a launch amplitude of 1.04 V. 000: Corresponds to a launch amplitude of 0.88 V. After updated: 011: Corresponds to a launch amplitude of 0.844 V. 100: Corresponds to a launch amplitude of 1.008 V. 101: Corresponds to a launch amplitude of 1.156 V. This will correct it accordingly. Fixes: b2e75563dc39 ("dt-bindings: phy: imx8mq-usb: add phy tuning properties") Cc: stable@vger.kernel.org Reviewed-by: Jun Li Signed-off-by: Xu Yang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml index daee0c0fc915..c468207eb951 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -63,8 +63,7 @@ properties: fsl,phy-tx-vboost-level-microvolt: description: Adjust the boosted transmit launch pk-pk differential amplitude - minimum: 880 - maximum: 1120 + enum: [844, 1008, 1156] fsl,phy-comp-dis-tune-percent: description: -- cgit v1.2.3-59-g8ed1b From 7325e0995f414af1cfa38be965dc47248cb4ec45 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 30 Apr 2025 17:45:00 +0800 Subject: dt-bindings: phy: imx8mq-usb: add imx95 tuning support The parameter value of below 3 properties are USB PHY specific. i.MX8MP and i.MX95 USB PHY has different meanings. This will enlarge parameters value and add constraints for them. - fsl,phy-tx-vref-tune-percent - fsl,phy-tx-rise-tune-percent - fsl,phy-comp-dis-tune-percent Reviewed-by: Jun Li Signed-off-by: Xu Yang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul --- .../bindings/phy/fsl,imx8mq-usb-phy.yaml | 34 ++++++++++++++++++++-- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml index c468207eb951..22dd91591a09 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -43,15 +43,15 @@ properties: fsl,phy-tx-vref-tune-percent: description: Tunes the HS DC level relative to the nominal level - minimum: 94 + minimum: 90 maximum: 124 fsl,phy-tx-rise-tune-percent: description: Adjusts the rise/fall time duration of the HS waveform relative to its nominal value - minimum: 97 - maximum: 103 + minimum: 90 + maximum: 120 fsl,phy-tx-preemp-amp-tune-microamp: description: @@ -111,6 +111,34 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + enum: + - fsl,imx8mq-usb-phy + - fsl,imx8mp-usb-phy + then: + properties: + fsl,phy-tx-vref-tune-percent: + minimum: 94 + fsl,phy-tx-rise-tune-percent: + minimum: 97 + maximum: 103 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usb-phy + then: + properties: + fsl,phy-tx-vref-tune-percent: + maximum: 108 + fsl,phy-comp-dis-tune-percent: + minimum: 94 + maximum: 104 + - if: required: - orientation-switch -- cgit v1.2.3-59-g8ed1b From 1d6fc048b86b76db73073ded8e84b0fd8757c908 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 14 Apr 2025 20:18:23 -0500 Subject: dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the example to the GRF binding as that has the complete block. Signed-off-by: Rob Herring (Arm) Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org Signed-off-by: Vinod Koul --- .../bindings/phy/rockchip,rk3399-pcie-phy.yaml | 45 ++++++++++++++++++++++ .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 36 ----------------- .../devicetree/bindings/soc/rockchip/grf.yaml | 13 ++++++- 3 files changed, 56 insertions(+), 38 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml new file mode 100644 index 000000000000..f46f065e5dbe --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3399-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 PCIE PHY + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: rockchip,rk3399-pcie-phy + + '#phy-cells': + oneOf: + - const: 0 + deprecated: true + - const: 1 + description: One lane per phy mode + + clocks: + maxItems: 1 + + clock-names: + const: refclk + + resets: + maxItems: 1 + + reset-names: + const: phy + +required: + - compatible + - '#phy-cells' + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt deleted file mode 100644 index b496042f1f44..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Rockchip PCIE PHY ------------------------ - -Required properties: - - compatible: rockchip,rk3399-pcie-phy - - clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must be "refclk" - - resets: Must contain an entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must be "phy" - -Required properties for legacy PHY mode (deprecated): - - #phy-cells: must be 0 - -Required properties for per-lane PHY mode (preferred): - - #phy-cells: must be 1 - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - - ... - - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - #phy-cells = <0>; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - resets = <&cru SRST_PCIEPHY>; - reset-names = "phy"; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2f61c1b95fea..fc328c4a35e4 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -201,8 +201,8 @@ allOf: pcie-phy: type: object - description: - Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt + $ref: /schemas/phy/rockchip,rk3399-pcie-phy.yaml# + unevaluatedProperties: false patternProperties: "^phy@[0-9a-f]+$": @@ -326,6 +326,15 @@ examples: #phy-cells = <0>; }; + pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; + phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x20>; -- cgit v1.2.3-59-g8ed1b From 59cf7546079e3d08d105369c48f8834970290082 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 4 May 2025 17:45:18 +0300 Subject: dt-bindings: phy: add exynos2200 eusb2 phy support Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, the driver doesn't make use of reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/samsung,exynos2200-eusb2-phy.yaml | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml new file mode 100644 index 000000000000..5e7e1bc2e39a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-eusb2-phy.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos2200-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 eUSB2 phy controller + +maintainers: + - Ivaylo Ivanov + +description: + Samsung Exynos2200 eUSB2 phy, based on Synopsys eUSB2 IP block, supports + LS/FS/HS usb connectivity. + +properties: + compatible: + enum: + - samsung,exynos2200-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: Reference clock + - description: Bus (APB) clock + - description: Control clock + + clock-names: + items: + - const: ref + - const: bus + - const: ctrl + + resets: + maxItems: 1 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 to USB 2.0 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + +additionalProperties: false + +examples: + - | + usb_hsphy: phy@10ab0000 { + compatible = "samsung,exynos2200-eusb2-phy"; + reg = <0x10ab0000 0x10000>; + #phy-cells = <0>; + + clocks = <&cmu_hsi0 7>, + <&cmu_hsi0 5>, + <&cmu_hsi0 8>; + clock-names = "ref", "bus", "ctrl"; + + vdd-supply = <&vreg_0p88>; + vdda12-supply = <&vreg_1p2>; + }; -- cgit v1.2.3-59-g8ed1b From e4c9a7b475e5d0d9b2440ee48f91d1364eabd6cb Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 4 May 2025 17:45:19 +0300 Subject: dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support Document support for Exynos2200. As the USBDRD 3.2 4nm controller consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will be handled by external drivers, define only the bus clocked used by the link controller. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 38 +++++++++++++++++++--- 1 file changed, 34 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index fdddddc7d611..cc60d2f6f70e 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -26,6 +26,7 @@ properties: compatible: enum: - google,gs101-usb31drd-phy + - samsung,exynos2200-usb32drd-phy - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy @@ -34,24 +35,32 @@ properties: - samsung,exynos850-usbdrd-phy clocks: - minItems: 2 + minItems: 1 maxItems: 5 clock-names: - minItems: 2 + minItems: 1 maxItems: 5 description: | - At least two clocks:: + Typically two clocks: - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used for register access. - PHY reference clock (usually crystal clock), used for PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' - in the CMU. + in the CMU. It's not needed for Exynos2200. "#phy-cells": const: 1 + phys: + maxItems: 1 + description: + USBDRD-underlying high-speed PHY + + phy-names: + const: hs + port: $ref: /schemas/graph.yaml#/properties/port description: @@ -151,6 +160,27 @@ allOf: - vdda-usbdp-supply - vddh-usbdp-supply + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-usb32drd-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: phy + reg: + maxItems: 1 + reg-names: + maxItems: 1 + required: + - phys + - phy-names + - if: properties: compatible: -- cgit v1.2.3-59-g8ed1b From 31eebeef8cdd4c9bddc9d34053cab6553616d0b7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 14 Apr 2025 15:57:26 +0100 Subject: dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family The RZ/G2L family requires two clocks for USB2 PHY, which are already defined in the DTSI files. Add a constraint in the DT binding document to ensure validation with `dtbs_check`. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index af275cea3456..f8d15f239b18 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -107,6 +107,9 @@ allOf: contains: const: renesas,rzg2l-usb2-phy then: + properties: + clocks: + minItems: 2 required: - resets -- cgit v1.2.3-59-g8ed1b From 9c4fbefc962dd13694b4a5051f432ed435c92220 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 14 Apr 2025 15:57:27 +0100 Subject: dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC. RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it needs additional configuration to be done as compared RZ/G2L USB2.0 phy. To handle this difference a SoC specific compat string is added for RZ/V2H(P) SoC. Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets` property and has two clocks. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index f8d15f239b18..2822dce8d9f4 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -16,6 +16,7 @@ properties: - enum: - renesas,usb2-phy-r8a77470 # RZ/G1C - renesas,usb2-phy-r9a08g045 # RZ/G3S + - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) - items: - enum: @@ -105,7 +106,9 @@ allOf: properties: compatible: contains: - const: renesas,rzg2l-usb2-phy + enum: + - renesas,usb2-phy-r9a09g057 + - renesas,rzg2l-usb2-phy then: properties: clocks: -- cgit v1.2.3-59-g8ed1b From d78b565371314e48242cb9383d0f9d331119ab2e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 3 May 2025 22:15:10 +0200 Subject: dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible Add compatible for the USB2 phy in the Rockchip RK3036 SoC. Apart from some bits that got swapped around in the phy registers, the block is nearly the same as the one on the rk3128. Signed-off-by: Heiko Stuebner Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 6a7ef556414c..7bcefe8c22d1 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -13,6 +13,7 @@ properties: compatible: enum: - rockchip,px30-usb2phy + - rockchip,rk3036-usb2phy - rockchip,rk3128-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3308-usb2phy @@ -184,6 +185,7 @@ allOf: contains: enum: - rockchip,px30-usb2phy + - rockchip,rk3036-usb2phy - rockchip,rk3128-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3308-usb2phy -- cgit v1.2.3-59-g8ed1b From abf55cdf9c5e58bac1feaff2e21bec43b898746c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 15 Apr 2025 13:00:04 +0800 Subject: dt-bindings: phy: rockchip,inno-usb2phy: add rk3562 Add compatible for the USB2 phy in the Rockchip RK3562 SoC. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 7bcefe8c22d1..58e735b5dd05 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3576-usb2phy - rockchip,rk3588-usb2phy @@ -192,6 +193,7 @@ allOf: - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3588-usb2phy - rockchip,rv1108-usb2phy -- cgit v1.2.3-59-g8ed1b