diff options
Diffstat (limited to 'drivers/watchdog/f71808e_wdt.c')
| -rw-r--r-- | drivers/watchdog/f71808e_wdt.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c index 9a1c761258ce..041172e6c469 100644 --- a/drivers/watchdog/f71808e_wdt.c +++ b/drivers/watchdog/f71808e_wdt.c @@ -338,8 +338,11 @@ static int f71862fg_pin_configure(unsigned short ioaddr) static int watchdog_start(void) { + int err; + u8 tmp; + /* Make sure we don't die as soon as the watchdog is enabled below */ - int err = watchdog_keepalive(); + err = watchdog_keepalive(); if (err) return err; @@ -386,19 +389,18 @@ static int watchdog_start(void) break; case f81866: - /* Set pin 70 to WDTRST# */ - superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, - BIT(3) | BIT(0)); - superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, - BIT(2)); /* * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0. * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch: * BIT5: 0 -> WDTRST# * 1 -> GPIO15 */ - superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, - BIT(5)); + tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL); + tmp &= ~(BIT(3) | BIT(0)); + tmp |= BIT(2); + superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp); + + superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5); break; default: @@ -525,7 +527,7 @@ static int watchdog_open(struct inode *inode, struct file *file) __module_get(THIS_MODULE); watchdog.expect_close = 0; - return nonseekable_open(inode, file); + return stream_open(inode, file); } static int watchdog_release(struct inode *inode, struct file *file) |