<feed xmlns='http://www.w3.org/2005/Atom'>
<title>qemu/docs/specs, branch master</title>
<subtitle>QEMU development tree</subtitle>
<id>https://git.zx2c4.com/qemu/atom/docs/specs?h=master</id>
<link rel='self' href='https://git.zx2c4.com/qemu/atom/docs/specs?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/'/>
<updated>2024-08-09T16:37:54Z</updated>
<entry>
<title>docs/specs/rocker.txt: Convert to rST</title>
<updated>2024-08-09T16:37:54Z</updated>
<author>
<name>Peter Maydell</name>
<email>peter.maydell@linaro.org</email>
</author>
<published>2024-08-09T16:37:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=9ca6876dc0befcc07b1c609dd96fa719feb7a318'/>
<id>urn:sha1:9ca6876dc0befcc07b1c609dd96fa719feb7a318</id>
<content type='text'>
Convert the rocker.txt specification document to rST format.  We make
extensive use of the :: marker to introduce a literal block for all
the tables and ASCII art, rather than trying to convert the tables to
rST table syntax.  This produces a valid rST document without needing
a huge diff.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-id: 20240801170131.3977807-2-peter.maydell@linaro.org
</content>
</entry>
<entry>
<title>docs/specs/pci-ids: Fix markup</title>
<updated>2024-08-06T14:24:14Z</updated>
<author>
<name>George Matsumura</name>
<email>gorg@gorgnet.net</email>
</author>
<published>2024-08-05T03:10:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=7e7085da1f86655cb9c892e14328cc07fe552717'/>
<id>urn:sha1:7e7085da1f86655cb9c892e14328cc07fe552717</id>
<content type='text'>
This fixes the markup of the PCI and PCIe Expander Bridge entries to be
consistent with the rest of the file.

Signed-off-by: George Matsumura &lt;gorg@gorgnet.net&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-ID: &lt;20240805031012.16547-4-gorg@gorgnet.net&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>docs/specs/pci-ids: Add missing devices</title>
<updated>2024-08-06T14:24:14Z</updated>
<author>
<name>George Matsumura</name>
<email>gorg@gorgnet.net</email>
</author>
<published>2024-08-05T03:10:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=6e717a723073fc05a8438d8ffb289e030207ee62'/>
<id>urn:sha1:6e717a723073fc05a8438d8ffb289e030207ee62</id>
<content type='text'>
Add the missing devices 1b36:000c (PCIe root port) and 1b36:000e
(PCIe-to-PCI bridge).

Signed-off-by: George Matsumura &lt;gorg@gorgnet.net&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-ID: &lt;20240805031012.16547-2-gorg@gorgnet.net&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging</title>
<updated>2024-07-24T01:25:40Z</updated>
<author>
<name>Richard Henderson</name>
<email>richard.henderson@linaro.org</email>
</author>
<published>2024-07-24T01:25:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=43f59bf76535b8842a762f8625b96091611aac11'/>
<id>urn:sha1:43f59bf76535b8842a762f8625b96091611aac11</id>
<content type='text'>
* target/i386/kvm: support for reading RAPL MSRs using a helper program
* hpet: emulation improvements

# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmaelL4UHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroMXoQf+K77lNlHLETSgeeP3dr7yZPOmXjjN
# qFY/18jiyLw7MK1rZC09fF+n9SoaTH8JDKupt0z9M1R10HKHLIO04f8zDE+dOxaE
# Rou3yKnlTgFPGSoPPFr1n1JJfxtYlLZRoUzaAcHUaa4W7JR/OHJX90n1Rb9MXeDk
# jV6P0v1FWtIDdM6ERm9qBGoQdYhj6Ra2T4/NZKJFXwIhKEkxgu4yO7WXv8l0dxQz
# jE4fKotqAvrkYW1EsiVZm30lw/19duhvGiYeQXoYhk8KKXXjAbJMblLITSNWsCio
# 3l6Uud/lOxekkJDAq5nH3H9hCBm0WwvwL+0vRf3Mkr+/xRGvrhtmUdp8NQ==
# =00mB
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 23 Jul 2024 03:19:58 AM AEST
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini &lt;bonzini@gnu.org&gt;" [full]
# gpg:                 aka "Paolo Bonzini &lt;pbonzini@redhat.com&gt;" [full]

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  hpet: avoid timer storms on periodic timers
  hpet: store full 64-bit target value of the counter
  hpet: accept 64-bit reads and writes
  hpet: place read-only bits directly in "new_val"
  hpet: remove unnecessary variable "index"
  hpet: ignore high bits of comparator in 32-bit mode
  hpet: fix and cleanup persistence of interrupt status
  Add support for RAPL MSRs in KVM/Qemu
  tools: build qemu-vmsr-helper
  qio: add support for SO_PEERCRED for socket channel
  target/i386: do not crash if microvm guest uses SGX CPUID leaves

Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/nvme: Add SPDM over DOE support</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Wilfred Mallawa</name>
<email>wilfred.mallawa@wdc.com</email>
</author>
<published>2024-07-03T09:20:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=4f947b10d525958578002848a92eeb6152ffbf0d'/>
<id>urn:sha1:4f947b10d525958578002848a92eeb6152ffbf0d</id>
<content type='text'>
Setup Data Object Exchange (DOE) as an extended capability for the NVME
controller and connect SPDM to it (CMA) to it.

Signed-off-by: Wilfred Mallawa &lt;wilfred.mallawa@wdc.com&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Acked-by: Klaus Jensen &lt;k.jensen@samsung.com&gt;
Message-Id: &lt;20240703092027.644758-4-alistair.francis@wdc.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>hw/acpi: Update ACPI GED framework to support vCPU Hotplug</title>
<updated>2024-07-23T00:15:41Z</updated>
<author>
<name>Salil Mehta</name>
<email>salil.mehta@huawei.com</email>
</author>
<published>2024-07-16T11:14:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=06f1f4958be70f14f527d1f03d1e9a141650bbc5'/>
<id>urn:sha1:06f1f4958be70f14f527d1f03d1e9a141650bbc5</id>
<content type='text'>
ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the
_CRS object of GED to intimate OSPM about an event. Later then demultiplexes the
notified event by evaluating ACPI _EVT method to know the type of event. Use
ACPI GED to also notify the guest kernel about any CPU hot(un)plug events.

Note, GED interface is used by many hotplug events like memory hotplug, NVDIMM
hotplug and non-hotplug events like system power down event. Each of these can
be selected using a bit in the 32 bit GED IO interface. A bit has been reserved
for the CPU hotplug event.

ACPI CPU hotplug related initialization should only happen if ACPI_CPU_HOTPLUG
support has been enabled for particular architecture. Add cpu_hotplug_hw_init()
stub to avoid compilation break.

Co-developed-by: Keqian Zhu &lt;zhukeqian1@huawei.com&gt;
Signed-off-by: Keqian Zhu &lt;zhukeqian1@huawei.com&gt;
Signed-off-by: Salil Mehta &lt;salil.mehta@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Gavin Shan &lt;gshan@redhat.com&gt;
Reviewed-by: David Hildenbrand &lt;david@redhat.com&gt;
Reviewed-by: Shaoqin Huang &lt;shahuang@redhat.com&gt;
Tested-by: Vishnu Pajjuri &lt;vishnu@os.amperecomputing.com&gt;
Tested-by: Xianglai Li &lt;lixianglai@loongson.cn&gt;
Tested-by: Miguel Luis &lt;miguel.luis@oracle.com&gt;
Reviewed-by: Vishnu Pajjuri &lt;vishnu@os.amperecomputing.com&gt;
Tested-by: Zhao Liu &lt;zhao1.liu@intel.com&gt;
Reviewed-by: Zhao Liu &lt;zhao1.liu@intel.com&gt;
Message-Id: &lt;20240716111502.202344-4-salil.mehta@huawei.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Acked-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
</content>
</entry>
<entry>
<title>Add support for RAPL MSRs in KVM/Qemu</title>
<updated>2024-07-22T17:19:37Z</updated>
<author>
<name>Anthony Harivel</name>
<email>aharivel@redhat.com</email>
</author>
<published>2024-05-22T15:34:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=0418f90809aea5b375c859e744c8e8610e9be446'/>
<id>urn:sha1:0418f90809aea5b375c859e744c8e8610e9be446</id>
<content type='text'>
Starting with the "Sandy Bridge" generation, Intel CPUs provide a RAPL
interface (Running Average Power Limit) for advertising the accumulated
energy consumption of various power domains (e.g. CPU packages, DRAM,
etc.).

The consumption is reported via MSRs (model specific registers) like
MSR_PKG_ENERGY_STATUS for the CPU package power domain. These MSRs are
64 bits registers that represent the accumulated energy consumption in
micro Joules. They are updated by microcode every ~1ms.

For now, KVM always returns 0 when the guest requests the value of
these MSRs. Use the KVM MSR filtering mechanism to allow QEMU handle
these MSRs dynamically in userspace.

To limit the amount of system calls for every MSR call, create a new
thread in QEMU that updates the "virtual" MSR values asynchronously.

Each vCPU has its own vMSR to reflect the independence of vCPUs. The
thread updates the vMSR values with the ratio of energy consumed of
the whole physical CPU package the vCPU thread runs on and the
thread's utime and stime values.

All other non-vCPU threads are also taken into account. Their energy
consumption is evenly distributed among all vCPUs threads running on
the same physical CPU package.

To overcome the problem that reading the RAPL MSR requires priviliged
access, a socket communication between QEMU and the qemu-vmsr-helper is
mandatory. You can specified the socket path in the parameter.

This feature is activated with -accel kvm,rapl=true,path=/path/sock.sock

Actual limitation:
- Works only on Intel host CPU because AMD CPUs are using different MSR
  adresses.

- Only the Package Power-Plane (MSR_PKG_ENERGY_STATUS) is reported at
  the moment.

Signed-off-by: Anthony Harivel &lt;aharivel@redhat.com&gt;
Link: https://lore.kernel.org/r/20240522153453.1230389-4-aharivel@redhat.com
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>Revert "docs/specs/pvpanic: mark shutdown event as not implemented"</title>
<updated>2024-07-01T21:16:04Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas@t-8ch.de</email>
</author>
<published>2024-05-27T06:27:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=0c0cc13d319cf7b876f327fa1c5cc1866ad868cc'/>
<id>urn:sha1:0c0cc13d319cf7b876f327fa1c5cc1866ad868cc</id>
<content type='text'>
The missing functionality has been implemented now.

This reverts commit e739d1935c461d0668057e9dbba9d06f728d29ec.

Signed-off-by: Thomas Weißschuh &lt;thomas@t-8ch.de&gt;
Message-Id: &lt;20240527-pvpanic-shutdown-v8-8-5a28ec02558b@t-8ch.de&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>docs, tests: do not specify scsi=off</title>
<updated>2024-06-05T09:00:56Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2024-06-04T14:40:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=993e38020fddc65e7536c5e1469c22588e5a9f16'/>
<id>urn:sha1:993e38020fddc65e7536c5e1469c22588e5a9f16</id>
<content type='text'>
This has been the default forever.

Acked-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>docs/specs/pvpanic: mark shutdown event as not implemented</title>
<updated>2024-03-18T12:42:45Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas@t-8ch.de</email>
</author>
<published>2024-03-13T18:30:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=e739d1935c461d0668057e9dbba9d06f728d29ec'/>
<id>urn:sha1:e739d1935c461d0668057e9dbba9d06f728d29ec</id>
<content type='text'>
Mention the fact that this event is not yet implemented
to avoid confusion.
As requested by Michael.

Signed-off-by: Thomas Weißschuh &lt;thomas@t-8ch.de&gt;
Message-Id: &lt;20240313-pvpanic-note-v1-1-7f2571cdaedc@t-8ch.de&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
</feed>
