qemu/host/include/aarch64, branch master

util/bufferiszero: Split out host include files

2024-06-19T19:47:11Z

Split out host/bufferiszero.h.inc for x86, aarch64 and generic in order to avoid an overlong ifdef ladder. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

accel/tcg: Rename load-extract/store-insert headers using .h.inc suffix

2024-04-26T13:31:37Z

Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'store-insert-al16.h' as 'store-insert-al16.h.inc' and 'load-extract-al16-al8.h' as 'load-extract-al16-al8.h.inc'. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson Message-Id: <20240424173333.96148-3-philmd@linaro.org>

Merge tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu into staging

2023-09-19T17:20:54Z

*: Delete checks for old host definitions tcg/loongarch64: Generate LSX instructions fpu: Add conversions between bfloat16 and [u]int8 fpu: Handle m68k extended precision denormals properly accel/tcg: Improve cputlb i/o organization accel/tcg: Simplify tlb_plugin_lookup accel/tcg: Remove false-negative halted assertion tcg: Add gvec compare with immediate and scalar operand tcg/aarch64: Emit BTI insns at jump landing pads [Resolved conflict between CPUINFO_PMULL and CPUINFO_BTI. --Stefan] * tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu: (39 commits) tcg: Map code_gen_buffer with PROT_BTI tcg/aarch64: Emit BTI insns at jump landing pads util/cpuinfo-aarch64: Add CPUINFO_BTI tcg: Add tcg_out_tb_start backend hook fpu: Handle m68k extended precision denormals properly fpu: Add conversions between bfloat16 and [u]int8 accel/tcg: Introduce do_st16_mmio_leN accel/tcg: Introduce do_ld16_mmio_beN accel/tcg: Merge io_writex into do_st_mmio_leN accel/tcg: Merge io_readx into do_ld_mmio_beN accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1 accel/tcg: Merge cpu_transaction_failed into io_failed plugin: Simplify struct qemu_plugin_hwaddr accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed accel/tcg: Split out io_prepare and io_failed accel/tcg: Simplify tlb_plugin_lookup target/arm: Use tcg_gen_gvec_cmpi for compare vs 0 tcg: Add gvec compare with immediate and scalar operand tcg/loongarch64: Implement 128-bit load & store tcg/loongarch64: Lower rotli_vec to vrotri ... Signed-off-by: Stefan Hajnoczi

util/cpuinfo-aarch64: Add CPUINFO_BTI

2023-09-16T14:57:16Z

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

host/include/aarch64: Implement clmul.h

2023-09-15T13:57:00Z

Detect PMULL in cpuinfo; implement the accel hook. Acked-by: Ard Biesheuvel Tested-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

arm: spelling fixes

2023-07-25T14:13:53Z

Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell

host/include/aarch64: Implement aes-round.h

2023-07-08T06:30:17Z

Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson

accel/tcg: Add aarch64 store_atom_insert_al16

2023-05-30T16:51:12Z

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8

2023-05-30T16:51:12Z

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

qemu/atomic128: Add runtime test for FEAT_LSE2

2023-05-24T01:54:55Z

With FEAT_LSE2, load and store of int128 is directly supported. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson