qemu/host, branch masterQEMU development treehttps://git.zx2c4.com/qemu/atom/host?h=master2024-07-03T17:24:12Zutil/cpuinfo-riscv: Support host/cpuinfo.h for riscv2024-07-03T17:24:12ZRichard Hendersonrichard.henderson@linaro.org2024-06-27T04:54:47Zurn:sha1:b86c6ba689662256ea32f3e27927524ccb13f81d
Move detection code out of tcg, similar to other hosts.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Revert "host/i386: assume presence of SSE2"2024-06-28T12:44:51ZPaolo Bonzinipbonzini@redhat.com2024-06-18T15:34:48Zurn:sha1:87b8bde55dc1700f212b2249b9c150714df67369
This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Revert "host/i386: assume presence of POPCNT"2024-06-28T12:44:51ZPaolo Bonzinipbonzini@redhat.com2024-06-18T15:34:32Zurn:sha1:fe721c1948ef459caab106190276717bec252c88
This reverts commit 45ccdbcb24baf99667997fac5cf60318e5e7db51.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
util/bufferiszero: Add loongarch64 vector acceleration2024-06-19T19:47:11ZRichard Hendersonrichard.henderson@linaro.org2024-06-06T23:54:52Zurn:sha1:a96a4987385c2c0477bebffdc9a2d5ceabd43141
Use inline assembly because no release compiler allows
per-function selection of the ISA.
Tested-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
util/bufferiszero: Split out host include files2024-06-19T19:47:11ZRichard Hendersonrichard.henderson@linaro.org2024-06-06T03:58:37Zurn:sha1:2d32a5d2a06a524c5e7967f918c406ec99418a34
Split out host/bufferiszero.h.inc for x86, aarch64 and generic
in order to avoid an overlong ifdef ladder.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
util/loongarch64: Detect LASX vector support2024-06-19T17:55:12ZRichard Hendersonrichard.henderson@linaro.org2024-05-27T17:18:20Zurn:sha1:9d779187b86eee59899111978c6c1bd56076b1ed
Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
host/i386: assume presence of POPCNT2024-06-05T09:01:05ZPaolo Bonzinipbonzini@redhat.com2024-05-31T08:29:32Zurn:sha1:45ccdbcb24baf99667997fac5cf60318e5e7db51
QEMU now requires an x86-64-v2 host, which has the POPCNT instruction.
Use it freely in TCG-generated code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
host/i386: assume presence of SSE22024-06-05T09:01:05ZPaolo Bonzinipbonzini@redhat.com2024-05-31T09:02:46Zurn:sha1:b18236897ca15c3db1506d8edb9a191dfe51429c
QEMU now requires an x86-64-v2 host, which has SSE2.
Use it freely in buffer_is_zero.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
host/i386: assume presence of CMOV2024-06-05T09:01:05ZPaolo Bonzinipbonzini@redhat.com2024-05-31T08:14:48Zurn:sha1:e68e97ce55b3d17af22dd62c3b3dc72f761b0862
QEMU now requires an x86-64-v2 host, which always has CMOV.
Use it freely in TCG generated code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
host/i386: nothing looks at CPUINFO_SSE42024-06-05T09:01:05ZPaolo Bonzinipbonzini@redhat.com2024-05-31T09:02:04Zurn:sha1:72baef13b9dce71f20ae840d9951e559e14abf6d
The only user was the SSE4.1 variant of buffer_is_zero, which has
been removed; code to compute CPUINFO_SSE4 is dead.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>