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<title>qemu/include/hw/mips, branch master</title>
<subtitle>QEMU development tree</subtitle>
<id>https://git.zx2c4.com/qemu/atom/include/hw/mips?h=master</id>
<link rel='self' href='https://git.zx2c4.com/qemu/atom/include/hw/mips?h=master'/>
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<updated>2024-01-05T15:20:15Z</updated>
<entry>
<title>hw/mips: Inline 'bios.h' definitions</title>
<updated>2024-01-05T15:20:15Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>philmd@linaro.org</email>
</author>
<published>2023-11-22T14:34:58Z</published>
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<id>urn:sha1:1eb64c39d093a20f773e87fd4d0509a33476c707</id>
<content type='text'>
There is no universal BIOS, each machine needs a specific one.

Move the machine-specific definitions to each machine code and
remove this bogus header.

Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;20231122184334.18201-1-philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'</title>
<updated>2023-10-19T21:13:27Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>philmd@linaro.org</email>
</author>
<published>2023-10-09T11:58:39Z</published>
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<id>urn:sha1:30a8d3a14216e31f2539b00ff4e5df7f3a08ce89</id>
<content type='text'>
"hw/mips/cpudevs.h" contains declarations which are specific
to the MIPS architecture; it doesn't make sense for these to
be called from a non-MIPS architecture. Move the declarations
to "target/mips/cpu.h".

Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20231009171443.12145-2-philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/mips/bootloader: Handle buffers as opaque arrays</title>
<updated>2023-01-13T08:32:32Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>philmd@linaro.org</email>
</author>
<published>2022-11-02T15:24:39Z</published>
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<id>urn:sha1:cd5066f8618bc6c80ec9088923c58f4a42ab0e7a</id>
<content type='text'>
It is irrelevant to the API what the buffers to fill are made of.
In particular, some MIPS ISA have 16-bit wide instructions.

Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20221211204533.85359-2-philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register</title>
<updated>2022-10-31T10:32:45Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>philmd@linaro.org</email>
</author>
<published>2022-10-26T19:18:19Z</published>
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<id>urn:sha1:36d7487b2aa033e9792fb310c39d106ffcadaa4f</id>
<content type='text'>
When one of the $sp/$a[0..3] register is already set, we might
want bl_gen_jump_kernel() to NOT set it again. Pass a boolean
argument for each register, to allow to optionally set them.

Tested-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;20221026191821.28167-2-philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>Replace TARGET_WORDS_BIGENDIAN</title>
<updated>2022-04-06T08:50:37Z</updated>
<author>
<name>Marc-André Lureau</name>
<email>marcandre.lureau@redhat.com</email>
</author>
<published>2022-03-23T15:57:18Z</published>
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<id>urn:sha1:ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec</id>
<content type='text'>
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done
with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1,
and thus should always be defined to prevent misuse.

Signed-off-by: Marc-André Lureau &lt;marcandre.lureau@redhat.com&gt;
Suggested-by: Halil Pasic &lt;pasic@linux.ibm.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220323155743.1585078-8-marcandre.lureau@redhat.com&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>hw/mips/gt64xxx_pci: Resolve gt64120_register()</title>
<updated>2022-03-08T18:38:13Z</updated>
<author>
<name>Bernhard Beschow</name>
<email>shentey@gmail.com</email>
</author>
<published>2022-02-17T10:19:24Z</published>
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<id>urn:sha1:aa85a461efd5dc2b44102228db373dc77df826d7</id>
<content type='text'>
Now that gt64120_register() lost its pic parameter, there is an
opportunity to remove it. gt64120_register() is old style by wrapping
qdev API, and the new style is to use qdev directly. So take the
opportunity and modernize the code.

Suggested-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Signed-off-by: Bernhard Beschow &lt;shentey@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Message-Id: &lt;20220217101924.15347-8-shentey@gmail.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>malta: Move PCI interrupt handling from gt64xxx_pci to piix4</title>
<updated>2022-03-08T18:17:04Z</updated>
<author>
<name>Bernhard Beschow</name>
<email>shentey@gmail.com</email>
</author>
<published>2022-02-17T10:19:19Z</published>
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<id>urn:sha1:a7fc9880514fcbc96c9825f040296fa59d7b3ccc</id>
<content type='text'>
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.

Signed-off-by: Bernhard Beschow &lt;shentey@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220217101924.15347-3-shentey@gmail.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>hw/mips: Add a bootloader helper</title>
<updated>2021-02-21T17:41:04Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2021-01-27T06:54:21Z</published>
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<id>urn:sha1:3ebbf86128f5607831ba5a3dec8bac02271a9390</id>
<content type='text'>
Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20210127065424.114125-2-jiaxun.yang@flygoat.com&gt;
[PMD: Restricted bl_reg enum to C source,
      inverted bl_gen_write() args,
      added license in hw/mips/bootloader.h]
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>hw/mips: Move address translation helpers to target/mips/</title>
<updated>2020-12-13T18:58:54Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>f4bug@amsat.org</email>
</author>
<published>2020-12-06T19:29:00Z</published>
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<id>urn:sha1:2fd9c5ad4449c862932b21e8f6b4573cc50b9ae8</id>
<content type='text'>
Address translation is an architectural thing (not hardware
related). Move the helpers from hw/ to target/.

As physical address and KVM are specific to system mode
emulation, restrict this file to softmmu, so it doesn't
get compiled for user-mode emulation.

Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20201206233949.3783184-2-f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>hw/mips: Fix Lesser GPL version number</title>
<updated>2020-11-03T15:51:13Z</updated>
<author>
<name>Chetan Pant</name>
<email>chetan4windows@gmail.com</email>
</author>
<published>2020-10-16T14:35:09Z</published>
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<id>urn:sha1:d136ecc085283dc068ab55ec830af8d10b5f938d</id>
<content type='text'>
There is no "version 2" of the "Lesser" General Public License.
It is either "GPL version 2.0" or "Lesser GPL version 2.1".
This patch replaces all occurrences of "Lesser GPL version 2" with
"Lesser GPL version 2.1" in comment section.

Signed-off-by: Chetan Pant &lt;chetan4windows@gmail.com&gt;
Reviewed-by: Thomas Huth &lt;thuth@redhat.com&gt;
Message-Id: &lt;20201016143509.26692-1-chetan4windows@gmail.com&gt;
[PMD: Split hw/ vs target/]
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
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