<feed xmlns='http://www.w3.org/2005/Atom'>
<title>qemu/include/hw/misc, branch master</title>
<subtitle>QEMU development tree</subtitle>
<id>https://git.zx2c4.com/qemu/atom/include/hw/misc?h=master</id>
<link rel='self' href='https://git.zx2c4.com/qemu/atom/include/hw/misc?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/'/>
<updated>2024-07-21T05:46:38Z</updated>
<entry>
<title>aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoC</title>
<updated>2024-07-21T05:46:38Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2024-07-17T06:30:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=cc8bae6f6270c52c8f9854a83f9cefec3e5ec108'/>
<id>urn:sha1:cc8bae6f6270c52c8f9854a83f9cefec3e5ec108</id>
<content type='text'>
Bit SCU500[2] of the AST2600 controls the boot device of the SoC.

Future changes will configure this bit to boot from eMMC disk images
specially built for this purpose.

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Andrew Jeffery &lt;andrew@codeconstruct.com.au&gt;
Tested-by: Andrew Jeffery &lt;andrew@codeconstruct.com.au&gt;
Tested-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/misc: In STM32L4x5 EXTI, consolidate 2 constants</title>
<updated>2024-07-11T10:41:34Z</updated>
<author>
<name>Inès Varhol</name>
<email>ines.varhol@telecom-paris.fr</email>
</author>
<published>2024-07-07T08:58:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=27d405301a676beffea4c13f5108c344fa6b8165'/>
<id>urn:sha1:27d405301a676beffea4c13f5108c344fa6b8165</id>
<content type='text'>
Up until now, the EXTI implementation had 16 inbound GPIOs connected to
the 16 outbound GPIOs of STM32L4x5 SYSCFG.
The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART
devices which are already implemented in QEMU).
In order to connect USART devices to EXTI, this commit consolidates
constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and
`EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40).

Signed-off-by: Inès Varhol &lt;ines.varhol@telecom-paris.fr&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Message-id: 20240707085927.122867-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging</title>
<updated>2024-07-04T03:54:17Z</updated>
<author>
<name>Richard Henderson</name>
<email>richard.henderson@linaro.org</email>
</author>
<published>2024-07-04T03:54:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=1406b7fc4bbaab42133b1ef03270179746e91723'/>
<id>urn:sha1:1406b7fc4bbaab42133b1ef03270179746e91723</id>
<content type='text'>
virtio: features,fixes

A bunch of improvements:
- vhost dirty log is now only scanned once, not once per device
- virtio and vhost now support VIRTIO_F_NOTIFICATION_DATA
- cxl gained DCD emulation support
- pvpanic gained shutdown support
- beginning of patchset for Generic Port Affinity Structure
- s3 support
- friendlier error messages when boot fails on some illegal configs
- for vhost-user, VHOST_USER_SET_LOG_BASE is now only sent once
- part of vhost-user support for any POSIX system -
  not yet enabled due to qtest failures
- sr-iov VF setup code has been reworked significantly
- new tests, particularly for risc-v ACPI
- bugfixes

Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;

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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (85 commits)
  hw/pci: Replace -1 with UINT32_MAX for romsize
  pcie_sriov: Register VFs after migration
  pcie_sriov: Remove num_vfs from PCIESriovPF
  pcie_sriov: Release VFs failed to realize
  pcie_sriov: Reuse SR-IOV VF device instances
  pcie_sriov: Ensure VF function number does not overflow
  pcie_sriov: Do not manually unrealize
  hw/ppc/spapr_pci: Do not reject VFs created after a PF
  hw/ppc/spapr_pci: Do not create DT for disabled PCI device
  hw/pci: Rename has_power to enabled
  virtio-iommu: Clear IOMMUDevice when VFIO device is unplugged
  virtio: remove virtio_tswap16s() call in vring_packed_event_read()
  hw/cxl/events: Mark cxl-add-dynamic-capacity and cxl-release-dynamic-capcity unstable
  hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity.
  tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
  pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
  meson.build: Add RISC-V to the edk2-target list
  tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path
  tests/data/acpi: Move x86 ACPI tables under x86/${machine} path
  tests/qtest/bios-tables-test.c: Set "arch" for x86 tests
  ...

Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'hw-misc-20240702' of https://github.com/philmd/qemu into staging</title>
<updated>2024-07-02T14:11:47Z</updated>
<author>
<name>Richard Henderson</name>
<email>richard.henderson@linaro.org</email>
</author>
<published>2024-07-02T14:11:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=ff6d8490e33acf44ed8afd549e203a42d6f813b5'/>
<id>urn:sha1:ff6d8490e33acf44ed8afd549e203a42d6f813b5</id>
<content type='text'>
Misc HW patches queue

- Prevent NULL deref in sPAPR network model (Oleg)
- Automatic deprecation of versioned machine types (Daniel)
- Correct 'dump-guest-core' property name in hint (Akihiko)
- Prevent IRQ leak in MacIO IDE model (Mark)
- Remove dead #ifdef'ry related to unsupported macOS 12.0 (Akihiko)
- Remove "hw/hw.h" where unnecessary (Thomas)

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* tag 'hw-misc-20240702' of https://github.com/philmd/qemu: (22 commits)
  Remove inclusion of hw/hw.h from files that don't need it
  net/vmnet: Drop ifdef for macOS versions older than 12.0
  block/file-posix: Drop ifdef for macOS versions older than 12.0
  audio: Drop ifdef for macOS versions older than 12.0
  hvf: Drop ifdef for macOS versions older than 12.0
  hw/ide/macio: switch from using qemu_allocate_irq() to qdev input GPIOs
  system/physmem: Fix reference to dump-guest-core
  docs: document special exception for machine type deprecation &amp; removal
  hw/i386: remove obsolete manual deprecation reason string of i440fx machines
  hw/ppc: remove obsolete manual deprecation reason string of spapr machines
  hw: skip registration of outdated versioned machine types
  hw: set deprecation info for all versioned machine types
  include/hw: temporarily disable deletion of versioned machine types
  include/hw: add macros for deprecation &amp; removal of versioned machines
  hw/i386: convert 'q35' machine definitions to use new macros
  hw/i386: convert 'i440fx' machine definitions to use new macros
  hw/m68k: convert 'virt' machine definitions to use new macros
  hw/ppc: convert 'spapr' machine definitions to use new macros
  hw/s390x: convert 'ccw' machine definitions to use new macros
  hw/arm: convert 'virt' machine definitions to use new macros
  ...

Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Remove inclusion of hw/hw.h from files that don't need it</title>
<updated>2024-07-02T04:58:48Z</updated>
<author>
<name>Thomas Huth</name>
<email>thuth@redhat.com</email>
</author>
<published>2024-07-01T13:26:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=f0936cbc1d42410ccd58c042bc26fa33a23a77d6'/>
<id>urn:sha1:f0936cbc1d42410ccd58c042bc26fa33a23a77d6</id>
<content type='text'>
hw/hw.h only contains the prototype of hw_error() nowadays, so
files that don't use this function don't need to include this
header.

Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
Reviewed-by: Cédric Le Goater &lt;clg@redhat.com&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Message-ID: &lt;20240701132649.58345-1-thuth@redhat.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/ide/macio: switch from using qemu_allocate_irq() to qdev input GPIOs</title>
<updated>2024-07-02T04:58:48Z</updated>
<author>
<name>Mark Cave-Ayland</name>
<email>mark.cave-ayland@ilande.co.uk</email>
</author>
<published>2024-06-28T16:03:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=efb359346c7af62dfa86f7ae7d3717a098b239f5'/>
<id>urn:sha1:efb359346c7af62dfa86f7ae7d3717a098b239f5</id>
<content type='text'>
This prevents the IRQs from being leaked when the macio IDE device is used.

Signed-off-by: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Akihiko Odaki &lt;akihiko.odaki@daynix.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-ID: &lt;20240628160334.653168-1-mark.cave-ayland@ilande.co.uk&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/misc/pvpanic: add support for normal shutdowns</title>
<updated>2024-07-01T21:16:04Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas@t-8ch.de</email>
</author>
<published>2024-05-27T06:27:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=6269086b0179e3d70750672174ed7fbd29ac7eaa'/>
<id>urn:sha1:6269086b0179e3d70750672174ed7fbd29ac7eaa</id>
<content type='text'>
Shutdown requests are normally hardware dependent.
By extending pvpanic to also handle shutdown requests, guests can
submit such requests with an easily implementable and cross-platform
mechanism.

Acked-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
Signed-off-by: Thomas Weißschuh &lt;thomas@t-8ch.de&gt;
Message-Id: &lt;20240527-pvpanic-shutdown-v8-5-5a28ec02558b@t-8ch.de&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>hw/misc/pvpanic: centralize definition of supported events</title>
<updated>2024-07-01T21:16:04Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas@t-8ch.de</email>
</author>
<published>2024-05-27T06:27:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=9b13640da3f94c0fbacbae6d23bd91febfa44588'/>
<id>urn:sha1:9b13640da3f94c0fbacbae6d23bd91febfa44588</id>
<content type='text'>
The different components of pvpanic duplicate the list of supported
events. Move it to the shared header file to minimize changes when new
events are added.

MST: tweak: keep header included in pvpanic.c to avoid header
dependency, rebase.

Reviewed-by: Thomas Huth &lt;thuth@redhat.com&gt;
Reviewed-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
Signed-off-by: Thomas Weißschuh &lt;thomas@t-8ch.de&gt;
Message-Id: &lt;20240527-pvpanic-shutdown-v8-3-5a28ec02558b@t-8ch.de&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>hw/misc: In STM32L4x5 EXTI, correct configurable interrupts</title>
<updated>2024-07-01T14:40:54Z</updated>
<author>
<name>Inès Varhol</name>
<email>ines.varhol@telecom-paris.fr</email>
</author>
<published>2024-06-29T11:07:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=9c4887e3b68a362f2f5a4e86daab98a51b3b769e'/>
<id>urn:sha1:9c4887e3b68a362f2f5a4e86daab98a51b3b769e</id>
<content type='text'>
The implementation of configurable interrupts (interrupts supporting
edge selection) was incorrectly expecting alternating input levels :
this commits adds a new status field `irq_levels` to actually detect
edges.

Signed-off-by: Inès Varhol &lt;ines.varhol@telecom-paris.fr&gt;
Message-id: 20240629110800.539969-2-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/misc: Implement mailbox properties for customer OTP and device specific private keys</title>
<updated>2024-07-01T11:48:55Z</updated>
<author>
<name>Rayhan Faizel</name>
<email>rayhan.faizel@gmail.com</email>
</author>
<published>2024-05-19T09:41:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=5d5f1b60916aa6bbebe192d74acb762414377430'/>
<id>urn:sha1:5d5f1b60916aa6bbebe192d74acb762414377430</id>
<content type='text'>
Four mailbox properties are implemented as follows:
1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP
2. Device-specific private key: GET_PRIVATE_KEY and
SET_PRIVATE_KEY.

The customer OTP is located in the rows 36-43. The device-specific private key
is located in the rows 56-63.

The customer OTP can be locked with the magic numbers 0xffffffff 0xaffe0000
when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates
this lock, which is undocumented. The lock also applies to the device-specific
private key.

Signed-off-by: Rayhan Faizel &lt;rayhan.faizel@gmail.com&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
</content>
</entry>
</feed>
