qemu/include/hw/ppc, branch master

pnv/xive2: Dump more END state with 'info pic'

2024-07-25T23:51:33Z

Additional END state 'info pic' information as added. The 'ignore', 'crowd' and 'precluded escalation control' bits of an Event Notification Descriptor are all used when delivering an interrupt targeting a VP-group or crowd. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c

2024-07-25T23:51:33Z

Moving xive2_nvp_pic_print_info() to align with the other "pic_print_info" functions. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

pnv/xive: Support cache flush and queue sync inject with notifications

2024-07-25T23:51:20Z

Adds support for writing a completion notification byte in memory whenever a cache flush or queue sync inject operation is requested by software. QEMU does not cache any of the XIVE data that is in memory and therefore it simply writes the completion notification byte at the time that the operation is requested. Co-authored-by: Glenn Miles Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

hw/ppc: SPI controller wiring to P10 chip

2024-07-25T23:21:06Z

In this commit, create SPI controller on p10 chip and connect cs irq. The QOM tree of pnv-spi and seeprom are. /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[2] (pnv-spi) /pnv-spi-bus.2 (SSI) /xscom-spi[0] (memory-region) /machine (powernv10-machine) /peripheral-anon (container) /device[0] (25csm04) /WP#[0] (irq) /ssi-gpio-cs[0] (irq) (qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus" "/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2" Signed-off-by: Chalapathi V Reviewed-by: Glenn Miles Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

hw/ssi: Add SPI model

2024-07-25T23:21:06Z

SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller. All SPI function control is mapped into the SPI register space to enable full control by firmware. In this commit SPI configuration component is modelled which contains all SPI configuration and status registers as well as the hold registers for data to be sent or having been received. An existing QEMU SSI framework is used and SSI_BUS is created. Signed-off-by: Chalapathi V Reviewed-by: Caleb Schlossin Reviewed-by: Cédric Le Goater Reviewed-by: Glenn Miles [np: Fix FDT macro compile for qtest] Signed-off-by: Nicholas Piggin

ppc/pnv: Remove ppc target dependency from pnv_xscom.h

2024-07-25T23:21:06Z

In this commit target specific dependency from include/hw/ppc/pnv_xscom.h has been removed so that pnv_xscom.h can be included outside hw/ppc. Signed-off-by: Chalapathi V Reviewed-by: Cédric Le Goater Reviewed-by: Caleb Schlossin Signed-off-by: Nicholas Piggin

ppc/pnv: Add an LPAR per core machine option

2024-07-25T23:21:06Z

Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread" modes. In per-core mode, some SPRs and IPI doorbells are shared between threads in a core. In per-thread mode, supervisor and user state is not shared between threads. OpenPOWER systems after POWER8 use LPAR per thread mode, and it is required for KVM. Enterprise systems use LPAR per core mode, as they partition the machine by core. Implement a lpar-per-core machine option for powernv machines. This is fixed true for POWER8 machines, and defaults off for P9 and P10. With this change, powernv8 SMT now works sufficiently to run Linux, with a single socket. Multi-threaded KVM guests still have problems, as does multi-socket Linux boot. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

ppc/pnv: Implement POWER10 PC xscom registers for direct controls

2024-07-25T23:21:06Z

The PC unit in the processor core contains xscom registers that provide low level status and control of the CPU. This implements "direct controls", sufficient for skiboot firmware, which uses it to send NMI IPIs between CPUs. POWER10 is sufficiently different from POWER9 (particularly with respect to QME and special wakeup) that it is not trivial to implement POWER9 support by reusing the code. Signed-off-by: Nicholas Piggin

ppc/pnv: Add a CPU nmi and resume function

2024-07-25T23:21:06Z

Power CPUs have an execution control facility that can pause, resume, and cause NMIs, among other things. Add a function that will nmi a CPU and resume it if it was paused, in preparation for implementing the control facility. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

ppc/pnv: Add POWER10 ChipTOD quirk for big-core

2024-07-25T23:21:06Z

POWER10 has a quirk in its ChipTOD addressing that requires the even small-core to be selected even when programming the odd small-core. This allows skiboot chiptod init to run in big-core mode. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin