qemu/target/alpha, branch masterQEMU development treehttps://git.zx2c4.com/qemu/atom/target/alpha?h=master2024-07-11T10:41:34Ztarget: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation2024-07-11T10:41:34ZPeter Maydellpeter.maydell@linaro.org2024-07-04T15:57:10Zurn:sha1:4f7b1ecba81c9dab8066e891ead8a4fff95781af
Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it
is not set then the default is to call the CPUClass::has_work
method (which has an identical function signature).
We would like to make the cpu_exec_halt method mandatory so we can
remove the runtime check and fallback handling. In preparation for
that, make all the targets which don't need special handling in their
cpu_exec_halt set it to their cpu_has_work implementation instead of
leaving it unset. (This is every target except for arm and i386.)
In the riscv case this requires us to make the function not
be local to the source file it's defined in.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
accel/tcg: Provide default implementation of disas_log2024-05-15T06:55:18ZRichard Hendersonrichard.henderson@linaro.org2024-04-03T08:57:16Zurn:sha1:962a145cdcd118f19597c08939ca24fd6227bc36
Almost all of the disas_log implementations are identical.
Unify them within translator_loop.
Drop extra Priv/Virt logging from target/riscv.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
exec/cpu: Extract page-protection definitions to page-protection.h2024-05-06T09:17:15ZPhilippe Mathieu-Daudéphilmd@linaro.org2023-12-06T19:27:32Zurn:sha1:74781c0888e819552538593c0932d98ea16c766b
Extract page-protection definitions from "exec/cpu-all.h"
to "exec/page-protection.h".
The list of files requiring the new header was generated
using:
$ git grep -wE \
'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240427155714.53669-3-philmd@linaro.org>
target/alpha: Implement CF_PCREL2024-05-04T15:05:51ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:13Zurn:sha1:23bb086350c0de390f77dd034d775742314cabd7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-10-philmd@linaro.org>
target/alpha: Split out gen_pc_disp2024-05-04T15:05:51ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:12Zurn:sha1:b1a3eacf314ba829506f65c227b57676db4ddbac
Prepare for pcrel by not modifying cpu_pc before use,
in the case of JSR.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-9-philmd@linaro.org>
target/alpha: Split out gen_goto_tb2024-05-04T15:05:49ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:11Zurn:sha1:82b60d2509ddb9123c48ea773c58886b7dad22d7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org>
[PMD: Split bigger patch, part 5/5]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-8-philmd@linaro.org>
target/alpha: Simplify gen_bcond_internal()2024-05-04T15:02:57ZPhilippe Mathieu-Daudéphilmd@linaro.org2024-05-03T07:20:10Zurn:sha1:39482c2edcc9864cf694b8ea525b49693443f90a
Richard Henderson explained on IRC:
bcond_internal() used to insist that both branch
destination and branch fallthrough are use_goto_tb;
if not, we'd use movcond to compute an indirect jump.
But it's perfectly fine for e.g. the branch fallthrough
to use_goto_tb, and the branch destination to use
an indirect branch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org>
[PMD: Split bigger patch, part 4/5]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-7-philmd@linaro.org>
target/alpha: Return DISAS_NORETURN once2024-05-04T14:38:09ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:09Zurn:sha1:9804ab26d0f25cb9c97e34f96bb0fb2be0a9f677
Trivial change to make next commits easier to understand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org>
[PMD: Split bigger patch, part 3/5]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-6-philmd@linaro.org>
target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURN2024-05-04T14:38:09ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:08Zurn:sha1:c0fcd5612e84810fbc62b17fb99a0a4dd847b251
Inline DISAS_PC_UPDATED switch case from alpha_tr_tb_stop():
switch (ctx->base.is_jmp) {
...
case DISAS_PC_UPDATED:
tcg_gen_lookup_and_goto_ptr();
break;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org>
[PMD: Split bigger patch, part 2/5]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-5-philmd@linaro.org>
target/alpha: Use DISAS_NEXT definition instead of magic '0' value2024-05-04T14:38:08ZRichard Hendersonrichard.henderson@linaro.org2024-05-03T07:20:07Zurn:sha1:0cda93c9b55b1f865f92a2a2e189dcbaab485bb2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org>
[PMD: Split bigger patch, part 1/5]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240503072014.24751-4-philmd@linaro.org>