<feed xmlns='http://www.w3.org/2005/Atom'>
<title>qemu/tests/qtest, branch master</title>
<subtitle>QEMU development tree</subtitle>
<id>https://git.zx2c4.com/qemu/atom/tests/qtest?h=master</id>
<link rel='self' href='https://git.zx2c4.com/qemu/atom/tests/qtest?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/'/>
<updated>2024-08-26T08:58:11Z</updated>
<entry>
<title>tests/qtest: Delete previous boot file</title>
<updated>2024-08-26T08:58:11Z</updated>
<author>
<name>Akihiko Odaki</name>
<email>akihiko.odaki@daynix.com</email>
</author>
<published>2024-08-23T06:13:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=aee07f2563d27167935ae3557a9f435937eb3f9f'/>
<id>urn:sha1:aee07f2563d27167935ae3557a9f435937eb3f9f</id>
<content type='text'>
A test run may create boot files several times. Delete the previous boot
file before creating a new one.

Signed-off-by: Akihiko Odaki &lt;akihiko.odaki@daynix.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Message-ID: &lt;20240823-san-v4-7-a24c6dfa4ceb@daynix.com&gt;
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
</content>
</entry>
<entry>
<title>tests/qtest: Add pnv-spi-seeprom qtest</title>
<updated>2024-07-25T23:21:06Z</updated>
<author>
<name>Chalapathi V</name>
<email>chalapathi.v@linux.ibm.com</email>
</author>
<published>2024-06-26T09:05:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=533074918727c5fafb11a033fcccaac11ee0227b'/>
<id>urn:sha1:533074918727c5fafb11a033fcccaac11ee0227b</id>
<content type='text'>
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.

Signed-off-by: Chalapathi V &lt;chalapathi.v@linux.ibm.com&gt;
Acked-by: Cédric Le Goater &lt;clg@redhat.com&gt;
Reviewed-by: Caleb Schlossin &lt;calebs@linux.vnet.ibm.com&gt;
Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/pnv: Update Power10's cfam id to use Power10 DD2</title>
<updated>2024-07-25T23:21:06Z</updated>
<author>
<name>Aditya Gupta</name>
<email>adityag@linux.ibm.com</email>
</author>
<published>2024-05-02T06:27:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=977e789c4a8ed813d4ab03f17ea20a575bf20cd1'/>
<id>urn:sha1:977e789c4a8ed813d4ab03f17ea20a575bf20cd1</id>
<content type='text'>
Power10 DD1.0 was dropped in:

    commit 8f054d9ee825 ("ppc: Drop support for POWER9 and POWER10 DD1 chips")

Use the newer Power10 DD2 chips cfam id.

Signed-off-by: Aditya Gupta &lt;adityag@linux.ibm.com&gt;
Reviewed-by: Cédric Le Goater &lt;clg@redhat.com&gt;
Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
</content>
</entry>
<entry>
<title>crypto: Restrict pkix_asn1_tab[] to crypto-tls-x509-helpers.c</title>
<updated>2024-07-24T09:39:10Z</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
<email>philmd@linaro.org</email>
</author>
<published>2024-05-02T09:56:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=0e9bb8ad4d907d28aea8336d43ae990d87b1c834'/>
<id>urn:sha1:0e9bb8ad4d907d28aea8336d43ae990d87b1c834</id>
<content type='text'>
pkix_asn1_tab[] is only accessed by crypto-tls-x509-helpers.c,
rename pkix_asn1_tab.c as pkix_asn1_tab.c.inc and include it once.

Reviewed-by: Daniel P. Berrangé &lt;berrange@redhat.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
[berrange: updated MAINTAINERS for changed filename]
Signed-off-by: Daniel P. Berrangé &lt;berrange@redhat.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging</title>
<updated>2024-07-23T23:32:04Z</updated>
<author>
<name>Richard Henderson</name>
<email>richard.henderson@linaro.org</email>
</author>
<published>2024-07-23T23:32:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=5885bcef3d760e84d17eb4113e85f2aea0bd0582'/>
<id>urn:sha1:5885bcef3d760e84d17eb4113e85f2aea0bd0582</id>
<content type='text'>
virtio,pci,pc: features,fixes

pci: Initial support for SPDM Responders
cxl: Add support for scan media, feature commands, device patrol scrub
    control, DDR5 ECS control, firmware updates
virtio: in-order support
virtio-net: support for SR-IOV emulation (note: known issues on s390,
                                          might get reverted if not fixed)
smbios: memory device size is now configurable per Machine
cpu: architecture agnostic code to support vCPU Hotplug

Fixes, cleanups all over the place.

Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;

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# gpg: Signature made Tue 23 Jul 2024 10:16:31 AM AEST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin &lt;mst@kernel.org&gt;" [undefined]
# gpg:                 aka "Michael S. Tsirkin &lt;mst@redhat.com&gt;" [undefined]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (61 commits)
  hw/nvme: Add SPDM over DOE support
  backends: Initial support for SPDM socket support
  hw/pci: Add all Data Object Types defined in PCIe r6.0
  tests/acpi: Add expected ACPI AML files for RISC-V
  tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
  tests/acpi: Add empty ACPI data files for RISC-V
  tests/qtest/bios-tables-test.c: Remove the fall back path
  tests/acpi: update expected DSDT blob for aarch64 and microvm
  acpi/gpex: Create PCI link devices outside PCI root bridge
  tests/acpi: Allow DSDT acpi table changes for aarch64
  hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
  hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
  virtio-iommu: Add trace point on virtio_iommu_detach_endpoint_from_domain
  hw/vfio/common: Add vfio_listener_region_del_iommu trace event
  virtio-iommu: Remove the end point on detach
  virtio-iommu: Free [host_]resv_ranges on unset_iommu_devices
  virtio-iommu: Remove probe_done
  Revert "virtio-iommu: Clear IOMMUDevice when VFIO device is unplugged"
  gdbstub: Add helper function to unregister GDB register space
  physmem: Add helper function to destroy CPU AddressSpace
  ...

Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tests/acpi: Add expected ACPI AML files for RISC-V</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2024-07-16T14:43:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=e9c0d54f4aebeeeebf1124d6acd607e3015e0a51'/>
<id>urn:sha1:e9c0d54f4aebeeeebf1124d6acd607e3015e0a51</id>
<content type='text'>
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.

These are all new files being added for the first time. Hence, iASL diff
output is not added.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Acked-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
Message-Id: &lt;20240716144306.2432257-10-sunilvl@ventanamicro.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2024-07-16T14:43:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=5b966e548fb7a530431379bab053eb1d6fb25867'/>
<id>urn:sha1:5b966e548fb7a530431379bab053eb1d6fb25867</id>
<content type='text'>
Add basic ACPI table test case for RISC-V.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
Message-Id: &lt;20240716144306.2432257-9-sunilvl@ventanamicro.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>tests/acpi: Add empty ACPI data files for RISC-V</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2024-07-16T14:43:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=cc3ba2422554b63f30b697eb67143b5d48c5b7a3'/>
<id>urn:sha1:cc3ba2422554b63f30b697eb67143b5d48c5b7a3</id>
<content type='text'>
As per process documented (steps 1-3) in bios-tables-test.c, add empty
AML data files for RISC-V ACPI tables and add the entries in
bios-tables-test-allowed-diff.h.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
Message-Id: &lt;20240716144306.2432257-8-sunilvl@ventanamicro.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>tests/qtest/bios-tables-test.c: Remove the fall back path</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2024-07-16T14:43:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=329b327924f7e1a7a735c91b31f722708599e10f'/>
<id>urn:sha1:329b327924f7e1a7a735c91b31f722708599e10f</id>
<content type='text'>
The expected ACPI AML files are moved now under ${arch}/{machine} path.
Hence, there is no need to search in old path which didn't have ${arch}.
Remove the code which searches for the expected AML files under old path
as well.

Suggested-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Igor Mammedov &lt;imammedo@redhat.com&gt;
Message-Id: &lt;20240716144306.2432257-7-sunilvl@ventanamicro.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
<entry>
<title>tests/acpi: update expected DSDT blob for aarch64 and microvm</title>
<updated>2024-07-23T00:15:42Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2024-07-16T14:43:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/qemu/commit/?id=0af3dfa5c5590ae21d1f58a389968d4b90112fd7'/>
<id>urn:sha1:0af3dfa5c5590ae21d1f58a389968d4b90112fd7</id>
<content type='text'>
After PCI link devices are moved out of the scope of PCI root complex,
the DSDT files of machines which use GPEX, will change. So, update the
expected AML files with these changes for these machines.

Mainly, there are 2 changes.

1) Since the link devices are created now directly under _SB for all PCI
root bridges in the system, they should have unique names. So, instead
of GSIx, named those devices as LXXY where L means link, XX will have
PCI bus number and Y will have the INTx number (ex: L000 or L001). The
_PRT entries will also be updated to reflect this name change.

2) PCI link devices are moved from the scope of each PCI root bridge to
directly under _SB.

Below is the sample iASL difference for one such link device.

Scope (\_SB)
{
    Name (_HID, "LNRO0005")  // _HID: Hardware ID
    Name (_UID, 0x1F)  // _UID: Unique ID
    Name (_CCA, One)  // _CCA: Cache Coherency Attribute
    Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
    {
        Memory32Fixed (ReadWrite,
            0x0A003E00,         // Address Base
            0x00000200,         // Address Length
            )
        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
        {
            0x0000004F,
        }
    })

+   Device (L000)
+   {
+       Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)
+       Name (_UID, Zero)  // _UID: Unique ID
+       Name (_PRS, ResourceTemplate ()
+       {
+           Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+           {
+               0x00000023,
+           }
+       })
+       Name (_CRS, ResourceTemplate ()
+       {
+           Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+           {
+               0x00000023,
+           }
+       })
+       Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
+       {
+       }
+   }
+
      Device (PCI0)
      {
          Name (_HID, "PNP0A08" /* PCI Express Bus */)  // _HID: Hardware ID
          Name (_CID, "PNP0A03" /* PCI Bus */)  // _CID: Compatible ID
          Name (_SEG, Zero)  // _SEG: PCI Segment
          Name (_BBN, Zero)  // _BBN: BIOS Bus Number
          Name (_UID, Zero)  // _UID: Unique ID
          Name (_STR, Unicode ("PCIe 0 Device"))  // _STR: Description String
          Name (_CCA, One)  // _CCA: Cache Coherency Attribute
          Name (_PRT, Package (0x80)  // _PRT: PCI Routing Table
          {

              Package (0x04)
              {
                  0xFFFF,
                  Zero,
-                 GSI0,
+                 L000,
                  Zero
              },

               .....

          })

          Device (GSI0)
          {
              Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)
              Name (_UID, Zero)  // _UID: Unique ID
              Name (_PRS, ResourceTemplate ()
              {
                 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
                 {
                     0x00000023,
                 }
              })
              Name (_CRS, ResourceTemplate ()
              {
                 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
                 {
                     0x00000023,
                 }
              })
              Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
              {
              }
          }
      }
}

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Message-Id: &lt;20240716144306.2432257-6-sunilvl@ventanamicro.com&gt;
Reviewed-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
</content>
</entry>
</feed>
