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| author |   Richard Henderson <richard.henderson@linaro.org> | 2024-05-10 09:03:41 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-05-15 08:57:39 +0200 |
| commit | c9290dfebfdba5c13baa5e1f10e13a1c876b0643 (patch) | |
| tree | 240f7df3cd27cc828dcd454d8ec07d6a38cab8d8 /scripts/coverage/compare_gcov_json.py | |
| parent | accel/tcg: Remove cpu_ldsb_code / cpu_ldsw_code (diff) | |
| download | qemu-c9290dfebfdba5c13baa5e1f10e13a1c876b0643.tar.xz qemu-c9290dfebfdba5c13baa5e1f10e13a1c876b0643.zip | |
tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs
TCG register spill/fill uses tcg_out_ld/st with all types,
not necessarily going through INDEX_op_{ld,st}_vec.
Cc: qemu-stable@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Tested-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions