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| * | | linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT codePeter Maydell2024-04-252-287/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ever since the bFLT format support was added in 2006, there has been a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT which is supposedly for shared library support. This is not enabled and it's not possible to enable it, because if you do you'll run into the "#error needs checking" in the calc_reloc() function. Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of an "#error code needs checking" in load_flat_file(). This code is obviously unfinished and has never been used; nobody in the intervening 18 years has complained about this or fixed it, so just delete the dead code. If anybody ever wants the feature they can always pull it out of git, or (perhaps better) write it from scratch based on the current Linux bFLT loader rather than the one of 18 years ago. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240411115313.680433-1-peter.maydell@linaro.org
| * | | hw/dma: avoid apparent overflow in soc_dma_set_requestAnastasia Belova2024-04-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In soc_dma_set_request() we try to set a bit in a uint64_t, but we do it with "1 << ch->num", which can't set any bits past 31; any use for a channel number of 32 or more would fail due to integer overflow. This doesn't happen in practice for our current use of this code, because the worst case is when we call soc_dma_init() with an argument of 32 for the number of channels, and QEMU builds with -fwrapv so the shift into the sign bit is well-defined. However, it's obviously not the intended behaviour of the code. Add casts to force the shift to be done as 64-bit arithmetic, allowing up to 64 channels. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.") Signed-off-by: Anastasia Belova <abelova@astralinux.ru> Message-id: 20240409115301.21829-1-abelova@astralinux.ru [PMM: Edit commit message to clarify that this doesn't actually bite us in our current usage of this code.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMIJinjie Ruan2024-04-251-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the CPU implements FEAT_NMI, then turn on the NMI support in the GICv3 too. It's permitted to have a configuration with FEAT_NMI in the CPU (and thus NMI support in the CPU interfaces too) but no NMI support in the distributor and redistributor, but this isn't a very useful setup as it's close to having no NMI support at all. We don't need to gate the enabling of NMI in the GIC behind a machine version property, because none of our current CPUs implement FEAT_NMI, and '-cpu max' is not something we maintain migration compatibility across versions for. So we can always enable the GIC NMI support when the CPU has it. Neither hvf nor KVM support NMI in the GIC yet, so we don't enable it unless we're using TCG. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com [PMM: Update comment and commit message] Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Add FEAT_NMI to maxJinjie Ruan2024-04-252-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FEAT_NMI on the 'max' CPU. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Report the VINMI interruptJinjie Ruan2024-04-251-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In vCPU Interface, if the vIRQ has the non-maskable property, report vINMI to the corresponding vPE. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()Jinjie Ruan2024-04-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In CPU Interface, if the IRQ has the non-maskable property, report NMI to the corresponding PE. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Implement NMI interrupt priorityJinjie Ruan2024-04-253-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()Peter Maydell2024-04-253-12/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit should be set or clear according to the Non-maskable property. And the RPR priority should also update the NMI bit according to the APR priority NMI bit. By the way, add gicv3_icv_nmiar1_read trace event. If the hpp irq is a NMI, the icv iar read should return 1022 and trap for NMI again Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: use cs->nmi_support instead of cs->gic->nmi_support] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Add NMI handling CPU interface registersPeter Maydell2024-04-254-5/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for the register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. And the APR and RPR has NMI bits which should be handled correctly. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Separate out whether cpuif supports NMI from whether the GIC proper (IRI) supports NMI] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Implement GICD_INMIRJinjie Ruan2024-04-252-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3_redist: Implement GICR_INMIR0Jinjie Ruan2024-04-252-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Add irq non-maskable propertyJinjie Ruan2024-04-252-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A SPI, PPI or SGI interrupt can have non-maskable property. So maintain non-maskable property in PendingIrq and GICR/GICD. Since add new device state, it also needs to be migrated, so also save NMI info in vmstate_gicv3_cpu and vmstate_gicv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3Jinjie Ruan2024-04-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it an error to try to set has-nmi=true for the KVM GICv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Add has-nmi property to GICv3 deviceJinjie Ruan2024-04-254-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a property has-nmi to the GICv3 device, and use this to set the NMI bit in the GICD_TYPER register. This isn't visible to guests yet because the property defaults to false and we won't set it in the board code until we've landed all of the changes needed to implement FEAT_GICV3_NMI. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()Jinjie Ruan2024-04-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) come from the hcrx_el2.HCRX_VFNMI bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPUJinjie Ruan2024-04-251-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it is not GICv2. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/intc/arm_gicv3: Add external IRQ lines for NMIJinjie Ruan2024-04-253-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Handle PSTATE.ALLINT on taking an exceptionJinjie Ruan2024-04-251-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMIJinjie Ruan2024-04-252-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Add support for NMI in arm_phys_excp_target_el()Jinjie Ruan2024-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Add support for Non-maskable InterruptJinjie Ruan2024-04-255-16/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Support MSR access to ALLINTJinjie Ruan2024-04-251-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support ALLINT msr access as follow: mrs <xt>, ALLINT // read allint msr ALLINT, <xt> // write allint with imm Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Implement ALLINT MSR (immediate)Jinjie Ruan2024-04-254-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The EL0 check is necessary to ALLINT, and the EL1 check is necessary when imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Add support for FEAT_NMI, Non-maskable InterruptJinjie Ruan2024-04-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in ARMv8.8-A and ARM v9.3-A. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Add PSTATE.ALLINTJinjie Ruan2024-04-252-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to ELx, with or without superpriority is masked. As Richard suggested, place ALLINT bit in PSTATE in env->pstate. In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to PSTATE regardless of whether this is an illegal exception return or not. So handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit path of the exception_return helper. With the change, exception entry and return are automatically handled. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMIJinjie Ruan2024-04-252-1/+12
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | Merge tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu into stagingRichard Henderson2024-04-2543-422/+224
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Update OpenBSD CI image to 7.5 * Update/remove Ubuntu 20.04 CI jobs * Update (most) CentOS 8 CI jobs to CentOS 9 * Some clean-ups and improvements to travis.yml * Minor test fixes * s390x header clean-ups * Doc updates # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmYqbu4RHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWqeA//cFAzjjmayCRZzuwwCFH0ILPrMNViRLFc # ZuslNEFygDPl1H1wnw3MKzhHy1hbaC3gf30MjtejU61OMMyxS4exZd1rvw94a0cm # OEisE8UG52kRsqPwKPktB2bybgX3BZbrFEwp1P0DsvpLTX7wI5nOZyNR4zWOf5Ym # mODN/MjMFOhWjONOnNDRn4TbySQqolIQBTCq+f1J5Ej74V+p17aC5Fe3xhlFp8Ip # aRockPW6dLpNt26zx6kKvQSYtkyLgQJSeUUyUCgcla03yzNSuV/kJPUoW0ewa+q8 # DZg1Ru5WJ6O8lELQdYq630cmdwg3e9EeI6q/U/1A11auuLaafOBi0eZW9LdPlrqD # 6a+zwVn+ipyRdz8eRGZVRGdhJ6XT27YfFuKxdiu4BxnS0LRks4vDcXreIcQmiIUN # bg/zSp6snCpYf7+GlUReZXWnVx401nu59+BNNKUV0qIxdORNm8kwd9ZpSQwXP/nF # BMPhj2hoqvWb4C4r3WlTaSPlkJGhkb2lMLucjCbeGrdnmna0RFOFB301fllbpnVm # 11SRipMEfrj/G5qp4giPLcruzesvRaZm85nmwDyOQWxr5Q0KWWfBVXZMt+qqOckR # 2SUtLPd9nWruCy7KN15BrOWkmXc+OU8UFUqXIOvflkI6aF1bmFYRyrXgqX2q7QDT # kEfWnBvBqxw= # =1uVo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 07:55:42 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] * tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu: target/s390x: Remove KVM stubs in cpu_models.h tests/unit: Remove debug statements in test-nested-aio-poll.c docs/devel: fix minor typo in submitting-a-patch.rst hw/s390x: Include missing 'cpu.h' header tests: Update our CI to use CentOS Stream 9 instead of 8 tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update tests/lcitool/libvirt-ci: Update to the latest master branch tests: Remove Ubuntu 20.04 container .travis.yml: Do some more testing with Clang .travis.yml: Update the jobs to Ubuntu 22.04 .travis.yml: Remove the unused UNRELIABLE environment variable Revert ".travis.yml: Cache Avocado cache" tests/vm: update openbsd image to 7.5 docs: i386: pc: Update maximum CPU numbers for PC Q35 tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint` MAINTAINERS: update email of Peter Lieven Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/s390x: Remove KVM stubs in cpu_models.hPhilippe Mathieu-Daudé2024-04-251-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the calls are elided when KVM is not available, we can remove the stubs (which are never compiled). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240419090631.48055-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests/unit: Remove debug statements in test-nested-aio-poll.cPhilippe Mathieu-Daudé2024-04-251-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have been running this test for almost a year; it is safe to remove its debug statements, which clutter CI jobs output: ▶ 88/100 /nested-aio-poll OK io_read 0x16bb26158 io_poll_true 0x16bb26158 > io_poll_ready io_read 0x16bb26164 < io_poll_ready io_poll_true 0x16bb26158 io_poll_false 0x16bb26164 > io_poll_ready io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_poll_false 0x16bb26164 io_read 0x16bb26164 < io_poll_ready 88/100 qemu:unit / test-nested-aio-poll OK Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-ID: <20240422112246.83812-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | docs/devel: fix minor typo in submitting-a-patch.rstManos Pitsidianakis2024-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | s/Resolved:/Resolves:/ Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-ID: <20240422124128.4034482-1-manos.pitsidianakis@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | hw/s390x: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé2024-04-252-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "cpu.h" is implicitly included. Include it explicitly to avoid the following error when refactoring headers: hw/s390x/s390-stattrib.c:86:40: error: use of undeclared identifier 'TARGET_PAGE_SIZE' len = sac->peek_stattr(sas, addr / TARGET_PAGE_SIZE, buflen, vals); ^ hw/s390x/s390-stattrib.c:94:58: error: use of undeclared identifier 'TARGET_PAGE_MASK' addr / TARGET_PAGE_SIZE, len, addr & ~TARGET_PAGE_MASK); ^ hw/s390x/s390-stattrib.c:224:40: error: use of undeclared identifier 'TARGET_PAGE_BITS' qemu_put_be64(f, (start_gfn << TARGET_PAGE_BITS) | STATTR_FLAG_MORE); ^ In file included from hw/s390x/s390-virtio-ccw.c:17: hw/s390x/s390-virtio-hcall.h:22:27: error: unknown type name 'CPUS390XState' int s390_virtio_hypercall(CPUS390XState *env); ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Eric Farman <farman@linux.ibm.com> Message-ID: <20240322162822.7391-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests: Update our CI to use CentOS Stream 9 instead of 8Thomas Huth2024-04-256-54/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RHEL 9 (and thus also the derivatives) have been available since two years now, so according to QEMU's support policy, we can drop the active support for the previous major version 8 now. Another reason for doing this is that Centos Stream 8 will go EOL soon: https://blog.centos.org/2023/04/end-dates-are-coming-for-centos-stream-8-and-centos-linux-7/ "After May 31, 2024, CentOS Stream 8 will be archived and no further updates will be provided." Thus upgrade our CentOS Stream container to major version 9 now. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240418101056.302103-5-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests/docker/dockerfiles: Run lcitool-refresh after the lcitool updateThomas Huth2024-04-2517-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This update adds the removing of the EXTERNALLY-MANAGED marker files that has been added to the lcitool recently. Quoting Daniel: "For those who don't know, python now commonly blocks the ability to run 'pip install' outside of a venv. This generally makes sense for a precious installation environment. Our containers are disposable though, so a venv has no benefit. Removing the 'EXTERNALLY-MANAGED' allows the historical arbitrary use of 'pip' outside a venv. lcitool just does this unconditionally given the containers are not precious." Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240418101056.302103-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests/lcitool/libvirt-ci: Update to the latest master branchThomas Huth2024-04-251-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need the latest fixes for the lcitool to be able to properly update our CentOS docker file to CentOS Stream 9. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240418101056.302103-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests: Remove Ubuntu 20.04 containerThomas Huth2024-04-252-158/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since Ubuntu 22.04 has now been available for more than two years, we can stop actively supporting the previous LTS version of Ubuntu now. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240418101056.302103-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | .travis.yml: Do some more testing with ClangThomas Huth2024-04-251-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are doing a lot of cross-compilation tests with GCC in the gitlab-CI already, so we could get some more test coverage by using Clang in the Travis-CI instead. Thus let's switch two additional jobs to use Clang for compilation. Message-ID: <20240320104144.823425-7-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | .travis.yml: Update the jobs to Ubuntu 22.04Thomas Huth2024-04-251-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to our support policy, we'll soon drop our official support for Ubuntu 20.04 ("Focal Fossa") in QEMU. Thus we should update the Travis jobs now to a newer release (Ubuntu 22.04 - "Jammy Jellyfish") for future testing. Since all jobs are using this release now, we can drop the entries from the individual jobs and use the global setting again. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240418101056.302103-6-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | .travis.yml: Remove the unused UNRELIABLE environment variableThomas Huth2024-04-251-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This variable was used to allow jobs to fail without spoiling the overall result. But the required "allow_failures:" hunk has been accidentally removed in commit 9d03f5abed ("travis.yml: Remove the "Release tarball" job"), and it was anyway only useful while we still had the x86 jobs here around that were our main CI jobs. Thus let's simply remove this useless variable now. Message-ID: <20240320104144.823425-6-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | Revert ".travis.yml: Cache Avocado cache"Thomas Huth2024-04-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c1073e44b46490133e16420e1784dec7bcd4e030. The Avocado tests have been removed from Travis a long time ago with commit c5008c76ee ("gitlab: add acceptance testing to system builds"), so we don't need to cache the avocado files here anymore. Message-ID: <20240320104144.823425-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests/vm: update openbsd image to 7.5Brad Smith2024-04-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | tests/vm: update openbsd to release 7.5 Signed-off-by: Brad Smith <brad@comstyle.com> Message-ID: <ZhaDVpNjq_ZifvPT@humpty.home.comstyle.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | docs: i386: pc: Update maximum CPU numbers for PC Q35Zhao Liu2024-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases the supported CPUs for PC Q35 machine. Update maximum CPU numbers for PC Q35 in the document. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240412085358.731560-1-zhao1.liu@linux.intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`Inès Varhol2024-04-2510-151/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The messages for assertions using hexadecimal numbers will be easier to understand with `g_assert_cmphex`. Cases changed : "cmpuint.*0x", "cmpuint.*<<" Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Message-ID: <20240414173349.31194-1-ines.varhol@telecom-paris.fr> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | MAINTAINERS: update email of Peter LievenPeter Lieven2024-04-251-3/+3
|/ / | | | | | | | | | | | | | | I will leave KAMP in the next days. Update email to stay reachable. Signed-off-by: Peter Lieven <pl@kamp.de> Message-ID: <20230105095039.182718-1-pl@kamp.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2024-04-2414-68/+107
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | meson: Make DEBUG_REMAP a meson option target/m68k: Support semihosting on non-ColdFire targets linux-user: do_setsockopt cleanups linux-user: Add FITRIM ioctl # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmYpjHcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+a/Af7BHmDB27U61b9i8et # cObewYH9y9M+iaCrIflNZPAaoguHDRKOuvw+PFT/dIo5FL2D509vYOuxUow1qLsy # q6b6kdvXROq9WU2NiuB86Abl/4mwwzxRhFah+Eh+OYSA2/pQnkcULkouLqxjFfF0 # xTBzZtHtYdTbCTVRbpd6XrwLo7Qrs85ovl4wVD1r+T2T8FkvrryoNOA/VjUWxyeh # 3b1X1I0wtOTnEA7JSr17JCXWZGENCmTO35r6WSYzJy5U/C59PjjgaaeMi3R3lQTJ # gg21EH0hlU1nTiPLg2ypj3l9NbIGAincAdDF/jufee+R75YSPdpKoDH8tUlUGsnM # CRx5Xg== # =J+5K # -----END PGP SIGNATURE----- # gpg: Signature made Wed 24 Apr 2024 03:49:27 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu: target/m68k: Support semihosting on non-ColdFire targets target/m68k: Perform the semihosting test during translate target/m68k: Pass semihosting arg to exit linux-user: Add FITRIM ioctl linux-user: do_setsockopt: eliminate goto in switch for SO_SNDTIMEO linux-user: do_setsockopt: make ip_mreq_source local to the place where it is used linux-user: do_setsockopt: make ip_mreq local to the place it is used and inline target_to_host_ip_mreq() linux-user: do_setsockopt: fix SOL_ALG.ALG_SET_KEY meson: Make DEBUG_REMAP a meson option Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/m68k: Support semihosting on non-ColdFire targetsKeith Packard2024-04-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the m68k semihosting spec: "The instruction used to trigger a semihosting request depends on the m68k processor variant. On ColdFire, "halt" is used; on other processors (which don't implement "halt"), "bkpt #0" may be used." Add support for non-CodeFire processors by matching BKPT #0 instructions. Signed-off-by: Keith Packard <keithp@keithp.com> [rth: Use semihosting_test()] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/m68k: Perform the semihosting test during translateRichard Henderson2024-04-243-17/+44
| | | | | | | | | | | | | | | | Replace EXCP_HALT_INSN by EXCP_SEMIHOSTING. Perform the pre- and post-insn tests during translate, leaving only the actual semihosting operation for the exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/m68k: Pass semihosting arg to exitKeith Packard2024-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | Instead of using d0 (the semihost function number), use d1 (the provide exit status). Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230802161914.395443-2-keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * linux-user: Add FITRIM ioctlMichael Vogt2024-04-243-0/+9
| | | | | | | | | | | | | | | | Tiny patch to add the missing FITRIM ioctl. Signed-off-by: Michael Vogt <mvogt@redhat.com> Message-Id: <20240403092048.16023-2-michael.vogt@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * linux-user: do_setsockopt: eliminate goto in switch for SO_SNDTIMEOMichael Tokarev2024-04-241-7/+4
| | | | | | | | | | | | | | | | | | | | | | There's identical code for SO_SNDTIMEO and SO_RCVTIMEO, currently implemented using an ugly goto into another switch case. Eliminate that using arithmetic if, making code flow more natural. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20240331100737.2724186-5-mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * linux-user: do_setsockopt: make ip_mreq_source local to the place where it is usedMichael Tokarev2024-04-241-2/+4
| | | | | | | | | | | | Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20240331100737.2724186-4-mjt@tls.msk.ru> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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