| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-04 | net: Remove receive_raw() |   Akihiko Odaki | 3 | -8/+12 |
| 2024-06-04 | net: Move virtio-net header length assertion | Akihiko Odaki | 2 | -3/+5 |
| 2024-06-04 | tap: Remove qemu_using_vnet_hdr() | Akihiko Odaki | 10 | -74/+5 |
| 2024-06-04 | tap: Remove tap_probe_vnet_hdr_len() | Akihiko Odaki | 6 | -42/+2 |
| 2024-06-03 | Merge tag 'pull-riscv-to-apply-20240603' of https://github.com/alistair23/qemu into staging |   Richard Henderson | 26 | -101/+543 |
| 2024-06-03 | iotests: test NBD+TLS+iothread |   Eric Blake | 2 | -0/+222 |
| 2024-06-03 | Merge tag 'pull-ufs-20240603' of https://gitlab.com/jeuk20.kim/qemu into staging | Richard Henderson | 4 | -21/+698 |
| 2024-06-03 | hw/ufs: Add support MCQ of UFSHCI 4.0 |   Minwoo Im | 4 | -19/+592 |
| 2024-06-03 | hw/ufs: Update MCQ-related fields to block/ufs.h | Minwoo Im | 1 | -2/+106 |
| 2024-06-03 | disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs |   Alistair Francis | 1 | -1/+64 |
| 2024-06-03 | riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() |   Daniel Henrique Barboza | 1 | -3/+3 |
| 2024-06-03 | target/riscv/kvm.c: Fix the hart bit setting of AIA |   Yong-Xuan Wang | 1 | -1/+8 |
| 2024-06-03 | target/riscv: rvzicbo: Fixup CBO extension register calculation | Alistair Francis | 1 | -4/+12 |
| 2024-06-03 | target/riscv: Remove experimental prefix from "B" extension |   Rob Bradford | 2 | -2/+2 |
| 2024-06-03 | target/riscv: do not set mtval2 for non guest-page faults |   Alexei Filippov | 1 | -6/+6 |
| 2024-06-03 | target/riscv: prioritize pmp errors in raise_mmu_exception() | Daniel Henrique Barboza | 1 | -10/+12 |
| 2024-06-03 | target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions |   Max Chou | 1 | -12/+4 |
| 2024-06-03 | target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w | Max Chou | 1 | -0/+1 |
| 2024-06-03 | target/riscv: rvv: Check single width operator for vector fp widen instructions | Max Chou | 1 | -0/+5 |
| 2024-06-03 | target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions | Max Chou | 1 | -2/+18 |
| 2024-06-03 | riscv: thead: Add th.sxstatus CSR emulation |   Christoph Müllner | 5 | -0/+85 |
| 2024-06-03 | target/riscv: Implement dynamic establishment of custom decoder |   Huang Tao | 5 | -16/+47 |
| 2024-06-03 | target/riscv/cpu.c: fix Zvkb extension config |   Yangyu Chen | 1 | -1/+1 |
| 2024-06-03 | target/riscv: Fix the element agnostic function problem | Huang Tao | 1 | -0/+22 |
| 2024-06-03 | target/riscv: Relax vector register check in RISCV gdbstub |   Jason Chien | 1 | -1/+1 |
| 2024-06-03 | target/riscv: Add support for Zve64x extension | Jason Chien | 3 | -6/+14 |
| 2024-06-03 | target/riscv: Add support for Zve32x extension | Jason Chien | 6 | -12/+15 |
| 2024-06-03 | trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint | Daniel Henrique Barboza | 1 | -0/+2 |
| 2024-06-03 | target/riscv/debug: set tval=pc in breakpoint exceptions | Daniel Henrique Barboza | 2 | -0/+4 |
| 2024-06-03 | target/riscv/kvm: tolerate KVM disable ext errors | Daniel Henrique Barboza | 1 | -4/+8 |
| 2024-06-03 | target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 |   Clément Léger | 1 | -1/+1 |
| 2024-06-03 | hw/riscv/boot.c: Support 64-bit address for initrd |   Cheng Yang | 1 | -2/+2 |
| 2024-06-03 | target/riscv/kvm: implement SBI debug console (DBCN) calls | Daniel Henrique Barboza | 2 | -0/+128 |
| 2024-06-03 | target/riscv: Raise exceptions on wrs.nto |   Andrew Jones | 3 | -9/+32 |
| 2024-06-03 | target/riscv/kvm: Fix exposure of Zkr | Andrew Jones | 3 | -4/+42 |
| 2024-06-03 | hw/intc/riscv_aplic: APLICs should add child earlier than realize |   yang.zhang | 1 | -4/+4 |
| 2024-05-31 | Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging | Richard Henderson | 33 | -1532/+2034 |
| 2024-05-31 | hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT |   David Hubbard | 2 | -0/+6 |
| 2024-05-30 | target/arm: Implement FEAT WFxT and enable for '-cpu max' |   Peter Maydell | 12 | -2/+180 |
| 2024-05-30 | accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt | Peter Maydell | 4 | -6/+21 |
| 2024-05-30 | docs/system/target-arm: Re-alphabetize board list | Peter Maydell | 1 | -3/+3 |
| 2024-05-30 | target/arm: Disable SVE extensions when SVE is disabled |   Marcin Juszkiewicz | 1 | -1/+5 |
| 2024-05-30 | target/arm: Convert FCSEL to decodetree | Richard Henderson | 2 | -63/+49 |
| 2024-05-30 | target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree | Richard Henderson | 2 | -148/+93 |
| 2024-05-30 | target/arm: Convert SQDMULH, SQRDMULH to decodetree | Richard Henderson | 4 | -196/+172 |
| 2024-05-30 | target/arm: Tidy SQDMULH, SQRDMULH (vector) | Richard Henderson | 4 | -39/+31 |
| 2024-05-30 | target/arm: Convert MLA, MLS to decodetree | Richard Henderson | 2 | -54/+31 |
| 2024-05-30 | target/arm: Convert MUL, PMUL to decodetree | Richard Henderson | 2 | -31/+25 |
| 2024-05-30 | target/arm: Convert SABA, SABD, UABA, UABD to decodetree | Richard Henderson | 2 | -16/+10 |
| 2024-05-30 | target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree | Richard Henderson | 2 | -16/+10 |
