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2024-07-19
hw/loongarch: Remove unimplemented extioi INT_encode mode
Song Gao
1
-1
/
+0
2024-07-19
target/loongarch/gdbstub: Add vector registers support
Song Gao
5
-4
/
+192
2024-07-19
Merge tag 'pull-target-arm-20240718' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
Richard Henderson
16
-245
/
+846
2024-07-18
hvf: arm: Do not advance PC when raising an exception
Akihiko Odaki
1
-0
/
+1
2024-07-18
tests/arm-cpu-features: Do not assume PMU availability
Akihiko Odaki
1
-5
/
+8
2024-07-18
tests/tcg/aarch64: Add test cases for SME FMOPA (widening)
Daniyal Khan
4
-2
/
+185
2024-07-18
target/arm: Use FPST_F16 for SME FMOPA (widening)
Richard Henderson
1
-4
/
+8
2024-07-18
target/arm: Use float_status copy in sme_fmopa_s
Daniyal Khan
1
-1
/
+1
2024-07-18
hw/arm/smmu: Refactor SMMU OAS
Mostafa Saleh
3
-23
/
+32
2024-07-18
hw/arm/smmuv3: Support and advertise nesting
Mostafa Saleh
1
-9
/
+26
2024-07-18
hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo
Mostafa Saleh
1
-7
/
+8
2024-07-18
hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova()
Mostafa Saleh
2
-15
/
+26
2024-07-18
hw/arm/smmu: Support nesting in the rest of commands
Mostafa Saleh
4
-3
/
+46
2024-07-18
hw/arm/smmu: Introduce smmu_iotlb_inv_asid_vmid
Mostafa Saleh
4
-10
/
+16
2024-07-18
hw/arm/smmu: Support nesting in smmuv3_range_inval()
Mostafa Saleh
4
-9
/
+66
2024-07-18
hw/arm/smmu-common: Support nested translation
Mostafa Saleh
3
-13
/
+82
2024-07-18
hw/arm/smmu-common: Add support for nested TLB
Mostafa Saleh
2
-4
/
+34
2024-07-18
hw/arm/smmu-common: Rework TLB lookup for nesting
Mostafa Saleh
1
-21
/
+43
2024-07-18
hw/arm/smmuv3: Translate CD and TT using stage-2 table
Mostafa Saleh
1
-17
/
+103
2024-07-18
hw/arm/smmu: Introduce CACHED_ENTRY_TO_ADDR
Mostafa Saleh
2
-2
/
+4
2024-07-18
hw/arm/smmu: Consolidate ASID and VMID types
Mostafa Saleh
4
-23
/
+23
2024-07-18
hw/arm/smmu: Split smmuv3_translate()
Mostafa Saleh
4
-121
/
+142
2024-07-18
hw/arm/smmu: Use enum for SMMU stage
Mostafa Saleh
3
-17
/
+25
2024-07-18
hw/arm/smmuv3: Fix encoding of CLASS in events
Mostafa Saleh
2
-1
/
+13
2024-07-18
hw/arm/smmu: Fix IPA for stage-2 events
Mostafa Saleh
2
-4
/
+10
2024-07-18
hw/arm/smmu-common: Add missing size check for stage-1
Mostafa Saleh
1
-0
/
+10
2024-07-18
hw/display/bcm2835_fb: fix fb_use_offsets condition
SamJakob
1
-1
/
+1
2024-07-18
target/arm: LDAPR should honour SCTLR_ELx.nAA
Peter Maydell
1
-1
/
+1
2024-07-18
target/arm: Fix handling of LDAPR/STLR with negative offset
Peter Maydell
1
-1
/
+1
2024-07-18
Merge tag 'pull-riscv-to-apply-20240718-1' of https://github.com/alistair23/qemu into staging
Richard Henderson
29
-210
/
+1245
2024-07-18
roms/opensbi: Update to v1.5
Daniel Henrique Barboza
3
-0
/
+0
2024-07-18
hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
Daniel Henrique Barboza
2
-0
/
+20
2024-07-18
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
Yu-Ming Chang
3
-9
/
+58
2024-07-18
target/riscv: Expose the Smcntrpmf config
Atish Patra
1
-0
/
+1
2024-07-18
target/riscv: Do not setup pmu timer if OF is disabled
Atish Patra
1
-12
/
+44
2024-07-18
target/riscv: More accurately model priv mode filtering.
Rajnesh Kanwal
3
-4
/
+33
2024-07-18
target/riscv: Start counters from both mhpmcounter and mcountinhibit
Rajnesh Kanwal
2
-24
/
+54
2024-07-18
target/riscv: Enforce WARL behavior for scounteren/hcounteren
Atish Patra
1
-2
/
+10
2024-07-18
target/riscv: Save counter values during countinhibit update
Atish Patra
3
-16
/
+24
2024-07-18
target/riscv: Implement privilege mode filtering for cycle/instret
Atish Patra
5
-37
/
+194
2024-07-18
target/riscv: Only set INH fields if priv mode is available
Atish Patra
1
-4
/
+25
2024-07-18
target/riscv: Add cycle & instret privilege mode filtering support
Kaiwen Xue
2
-1
/
+149
2024-07-18
target/riscv: Add cycle & instret privilege mode filtering definitions
Kaiwen Xue
2
-0
/
+35
2024-07-18
target/riscv: Add cycle & instret privilege mode filtering properties
Kaiwen Xue
2
-0
/
+2
2024-07-18
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
Atish Patra
1
-29
/
+38
2024-07-18
target/riscv: Combine set_mode and set_virt functions.
Rajnesh Kanwal
3
-41
/
+35
2024-07-18
target/riscv/kvm: update KVM regs to Linux 6.10-rc5
Daniel Henrique Barboza
1
-0
/
+2
2024-07-18
disas/riscv: Add decode for Zawrs extension
Balaji Ravikumar
1
-0
/
+6
2024-07-18
target/riscv: Validate the mode in write_vstvec
Jiayi Li
1
-1
/
+6
2024-07-18
disas/riscv: Support zabha disassemble
LIU Zhiwei
1
-0
/
+60
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