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2024-05-05Hexagon (target/hexagon) Remove gen_shortcode.pyTaylor Simpson4-81/+0
This data structure is not used Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240307032327.4799-9-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Remove gen_op_regs.pyTaylor Simpson3-138/+2
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-8-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Remove uses of op_regs_generated.h.incTaylor Simpson4-110/+13
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-7-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pairTaylor Simpson1-1/+15
Make sure the decoding of HVX .new is correctly handling this case Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-6-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark has_pred_dest in trans functionsTaylor Simpson3-0/+9
Check that the value matches opcode_wregs Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-5-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark dest_idx in trans functionsTaylor Simpson4-0/+11
Check that the value matches opcode_reginfo/opcode_wregs Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark new_read_idx in trans functionsTaylor Simpson4-6/+16
Check that the value matches opcode_reginfo Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-3-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Add is_old/is_new to Register classTaylor Simpson1-0/+12
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Only pass env to generated helper when neededTaylor Simpson3-8/+32
Currently, we pass env to every generated helper. When the semantics of the instruction only depend on the arguments, this is unnecessary and adds extra overhead to the helper call. We add the TCG_CALL_NO_RWG_SE flag to any non-HVX helpers that don't get the ptr to env. The A2_nop and SA1_setin1 instructions end up with no arguments. This results in a "old-style function definition" error from the compiler, so we write overrides for them. With this change, the number of helpers with env argument is idef-parser enabled: 329 total, 23 with env idef-parser disabled: 1543 total, 550 with env Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240214042726.19290-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Pass SP explicitly to helpers that need itTaylor Simpson3-2/+14
Rather than reading SP from the env, pass it explicitly Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240214042726.19290-3-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Pass P0 explicitly to helpers that need itTaylor Simpson2-2/+12
Rather than reading P0 from the env, pass it explicitly Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240214042726.19290-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Enable more short-circuit packets (HVX)Taylor Simpson4-95/+115
Look for read-after-write instead of overlap of reads and writes HVX instructions with helpers have pass-by-reference semantics, so we check for overlaps of reads and writes within the same instruction. Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240201103340.119081-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)Taylor Simpson2-23/+11
Look for read-after-write instead of overlap of reads and writes Here is an example with overalp but no read-after-write: 0x000200fc: 0x38103876 { R0 = add(R0,R1); R6 = add(R6,R7) } BEFORE: ---- 00000000000200fc mov_i32 loc2,$0x0 mov_i32 loc2,r0 add_i32 loc3,loc2,r1 mov_i32 loc2,loc3 mov_i32 loc4,$0x0 mov_i32 loc4,r6 add_i32 loc5,loc4,r7 mov_i32 loc4,loc5 mov_i32 r0,loc2 mov_i32 r6,loc4 AFTER: ---- 00000000000200fc add_i32 loc2,r0,r1 mov_i32 r0,loc2 add_i32 loc3,r6,r7 mov_i32 r6,loc3 We can also short-circuit packets with .new values by reading from the real destination instead of the temporary. 0x00020100: 0x78005ff3 { R19 = #0xff 0x00020104: 0x2002e204 if (cmp.eq(N19.new,R2)) jump:t PC+8 } BEFORE: ---- 0000000000020100 mov_i32 pc,$0x20108 mov_i32 loc8,$0x0 mov_i32 loc8,$0xff setcond_i32 loc10,loc8,r2,eq mov_i32 loc6,loc10 mov_i32 r19,loc8 add_i32 pkt_cnt,pkt_cnt,$0x2 add_i32 insn_cnt,insn_cnt,$0x4 brcond_i32 loc6,$0x0,eq,$L1 goto_tb $0x0 mov_i32 pc,$0x20108 exit_tb $0x7fbb54000040 set_label $L1 goto_tb $0x1 exit_tb $0x7fbb54000041 set_label $L0 exit_tb $0x7fbb54000043 AFTER: ---- 0000000000020100 mov_i32 pc,$0x20108 mov_i32 r19,$0xff setcond_i32 loc7,r19,r2,eq mov_i32 loc4,loc7 add_i32 pkt_cnt,pkt_cnt,$0x2 add_i32 insn_cnt,insn_cnt,$0x4 brcond_i32 loc4,$0x0,eq,$L1 goto_tb $0x0 mov_i32 pc,$0x20108 exit_tb $0x7f9764000040 set_label $L1 goto_tb $0x1 exit_tb $0x7f9764000041 set_label $L0 exit_tb $0x7f9764000043 Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240201103340.119081-3-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Analyze reads before writesTaylor Simpson4-49/+83
We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes We also create special versions of ctx_log_*_read for new operands Check that the operand is written before the read This is a precursor to improving the analysis for short-circuiting the packet semantics in a subsequent commit Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240201103340.119081-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-04target/alpha: Implement CF_PCRELRichard Henderson2-5/+47
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-10-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_pc_dispRichard Henderson1-18/+23
Prepare for pcrel by not modifying cpu_pc before use, in the case of JSR. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-9-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_goto_tbRichard Henderson1-37/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 5/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-8-philmd@linaro.org>
2024-05-04target/alpha: Simplify gen_bcond_internal()Philippe Mathieu-Daudé1-10/+9
Richard Henderson explained on IRC: bcond_internal() used to insist that both branch destination and branch fallthrough are use_goto_tb; if not, we'd use movcond to compute an indirect jump. But it's perfectly fine for e.g. the branch fallthrough to use_goto_tb, and the branch destination to use an indirect branch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 4/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-7-philmd@linaro.org>
2024-05-04target/alpha: Return DISAS_NORETURN onceRichard Henderson1-5/+4
Trivial change to make next commits easier to understand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 3/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-6-philmd@linaro.org>
2024-05-04target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURNRichard Henderson1-2/+4
Inline DISAS_PC_UPDATED switch case from alpha_tr_tb_stop(): switch (ctx->base.is_jmp) { ... case DISAS_PC_UPDATED: tcg_gen_lookup_and_goto_ptr(); break; Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 2/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-5-philmd@linaro.org>
2024-05-04target/alpha: Use DISAS_NEXT definition instead of magic '0' valueRichard Henderson1-2/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 1/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-4-philmd@linaro.org>
2024-05-04target/alpha: Hoist branch shift to initial decodeRichard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-3-philmd@linaro.org>
2024-05-04target/alpha: Use cpu_env in preference to ALPHA_CPURichard Henderson2-13/+10
ALPHA_CPU has a dynamic object type assert, which is unnecessary considering that these are all class hooks. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-2-philmd@linaro.org>
2024-05-03ui/cocoa.m: Drop old macOS-10.12-and-earlier compat ifdefsPeter Maydell1-13/+0
We only support the most recent two versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code already assumes at least macOS 12 Monterey or better, because it uses NSScreen safeAreaInsets, which is 12.0-or-newer. Remove the ifdefs that were providing backwards compatibility for building on 10.12 and earlier versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240502142904.62644-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for SUBV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how underflow is calculated. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240430163125.77430-5-philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for ADDV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how overflow is calculated. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-4-philmd@linaro.org>
2024-05-03target/sh4: Fix SUBV opcodePhilippe Mathieu-Daudé3-1/+34
The documentation says: SUBV Rm, Rn Rn - Rm -> Rn, underflow -> T The overflow / underflow can be calculated as: T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 However we were using the incorrect: T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31 Fix by using the Rn register instead of Rm. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2318 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-3-philmd@linaro.org>
2024-05-03target/sh4: Fix ADDV opcodePhilippe Mathieu-Daudé3-1/+31
The documentation says: ADDV Rm, Rn Rn + Rm -> Rn, overflow -> T But QEMU implementation was: ADDV Rm, Rn Rn + Rm -> Rm, overflow -> T Fix by filling the correct Rm register. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-2-philmd@linaro.org>
2024-05-03MAINTAINERS: Update my email addressAnthony PERARD1-1/+1
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240429154938.19340-1-anthony.perard@citrix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03plugins: Update stale commentPhilippe Mathieu-Daudé1-1/+1
"plugin_mask" was renamed as "event_mask" in commit c006147122 ("plugins: create CPUPluginState and migrate plugin_mask"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-03plugins/api: Only include 'exec/ram_addr.h' with system emulationPhilippe Mathieu-Daudé1-1/+1
"exec/ram_addr.h" shouldn't be used with user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-4-philmd@linaro.org>
2024-05-03coverity: Update user emulation regexpPhilippe Mathieu-Daudé1-1/+1
All user emulation headers are now under include/user/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-3-philmd@linaro.org>
2024-05-03user: Move 'thunk.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé5-6/+9
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-2-philmd@linaro.org>
2024-05-03user: Move 'abitypes.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé6-7/+7
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240503125202.35667-1-philmd@linaro.org>
2024-05-03exec: Include missing license in 'exec/cpu-common.h'Philippe Mathieu-Daudé1-2/+7
Commit 1ad2134f91 ("Hardware convenience library") extracted "cpu-common.h" from "cpu-all.h", which uses the LGPL-2.1+ license. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-5-philmd@linaro.org>
2024-05-03tests/bench: Add bufferiszero-benchRichard Henderson2-0/+48
Benchmark each acceleration function vs an aligned buffer of zeros. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Add simd acceleration for aarch64Richard Henderson1-0/+67
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely double-check with the compiler flags for __ARM_NEON and don't bother with a runtime check. Otherwise, model the loop after the x86 SSE2 function. Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and 2 cycles on neoverse-n1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Simplify test_buffer_is_zero_next_accelRichard Henderson1-46/+35
Because the three alternatives are monotonic, we don't need to keep a couple of bitmasks, just identify the strongest alternative at startup. Generalize test_buffer_is_zero_next_accel and init_accel by always defining an accel_table array. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Introduce biz_accel_fn typedefRichard Henderson1-3/+4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Improve scalar variantRichard Henderson1-34/+51
Split less-than and greater-than 256 cases. Use unaligned accesses for head and tail. Avoid using out-of-bounds pointers in loop boundary conditions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Optimize SSE2 and AVX2 variantsAlexander Monakov1-41/+76
Increase unroll factor in SIMD loops from 4x to 8x in order to move their bottlenecks from ALU port contention to load issue rate (two loads per cycle on popular x86 implementations). Avoid using out-of-bounds pointers in loop boundary conditions. Follow SSE2 implementation strategy in the AVX2 variant. Avoid use of PTEST, which is not profitable there (like in the removed SSE4 variant). Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-6-amonakov@ispras.ru>
2024-05-03util/bufferiszero: Remove useless prefetchesAlexander Monakov1-3/+0
Use of prefetching in bufferiszero.c is quite questionable: - prefetches are issued just a few CPU cycles before the corresponding line would be hit by demand loads; - they are done for simple access patterns, i.e. where hardware prefetchers can perform better; - they compete for load ports in loops that should be limited by load port throughput rather than ALU throughput. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-5-amonakov@ispras.ru>
2024-05-03util/bufferiszero: Reorganize for early test for accelerationAlexander Monakov2-52/+62
Test for length >= 256 inline, where is is often a constant. Before calling into the accelerated routine, sample three bytes from the buffer, which handles most non-zero buffers. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Message-Id: <20240206204809.9859-3-amonakov@ispras.ru> [rth: Use __builtin_constant_p; move the indirect call out of line.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Remove AVX512 variantAlexander Monakov1-35/+3
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD routines are invoked much more rarely in normal use when most buffers are non-zero. This makes use of AVX512 unprofitable, as it incurs extra frequency and voltage transition periods during which the CPU operates at reduced performance, as described in https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-4-amonakov@ispras.ru> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Remove SSE4.1 variantAlexander Monakov1-29/+0
The SSE4.1 variant is virtually identical to the SSE2 variant, except for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing if an SSE register is all zeroes. The PTEST instruction decodes to two uops, so it can be handled only by the complex decoder, and since CMP+JNE are macro-fused, both sequences decode to three uops. The uops comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch standpoint. Hence, the use of PTEST brings no benefit from throughput standpoint. Its latency is not important, since it feeds only a conditional jump, which terminates the dependency chain. I never observed PTEST variants to be faster on real hardware. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-2-amonakov@ispras.ru>
2024-05-03accel/whpx: Fix NULL dereference in whpx_init_vcpu()Philippe Mathieu-Daudé1-1/+1
When mechanically moving the @dirty field to AccelCPUState in commit 9ad49538c7, we neglected cpu->accel is still NULL when we want to dereference it. Fixes: 9ad49538c7 ("accel/whpx: Use accel-specific per-vcpu @dirty field") Reported-by: Volker Rümelin <vr_qemu@t-online.de> Suggested-by: Volker Rümelin <vr_qemu@t-online.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429091918.27429-2-philmd@linaro.org>
2024-05-03accel/nvmm: Fix NULL dereference in nvmm_init_vcpu()Philippe Mathieu-Daudé1-1/+1
When mechanically moving the @dirty field to AccelCPUState in commit 79f1926b2d, we neglected cpu->accel is still NULL when we want to dereference it. Reported-by: Volker Rümelin <vr_qemu@t-online.de> Suggested-by: Volker Rümelin <vr_qemu@t-online.de> Fixes: 79f1926b2d ("accel/nvmm: Use accel-specific per-vcpu @dirty field") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429091918.27429-3-philmd@linaro.org>
2024-05-01qga: Implement SSH commands for Windowsaidaleuc4-11/+749
Signed-off-by: Aidan Leuck <aidan_leuck@selinc.com> Tested-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20240424144029.30665-3-aidan_leuck@selinc.com Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-05-01qga: Refactor common SSH functionsaidaleuc4-47/+63
Message-Id: <20240424144029.30665-2-aidan_leuck@selinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit In preparation of a Windows implementation, move the non-POSIX specific code to commands-common-ssh. Signed-off-by: Aidan Leuck <aidan_leuck@selinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20240424144029.30665-2-aidan_leuck@selinc.com Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-05-01qga/commands-posix: qmp_guest_set_user_password: use ga_run_command helperAndrey Drobyshev1-83/+13
There's no need to check for the existence of the "chpasswd", "pw" executables, as the exec() call will do that for us. Signed-off-by: Andrey Drobyshev <andrey.drobyshev@virtuozzo.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20240320161648.158226-8-andrey.drobyshev@virtuozzo.com Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
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