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<title>rhel7-kernel-misery/include/linux/mtd, branch master</title>
<subtitle>Attempts to make the RHEL7 kernel work in minimal CI</subtitle>
<id>https://git.zx2c4.com/rhel7-kernel-misery/atom/include/linux/mtd?h=master</id>
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<updated>2020-09-30T14:24:59Z</updated>
<entry>
<title>linux-3.10.0-1160.el7</title>
<updated>2020-09-30T14:24:59Z</updated>
<author>
<name>Jason A. Donenfeld</name>
<email>Jason@zx2c4.com</email>
</author>
<published>2020-09-30T14:24:59Z</published>
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<id>urn:sha1:e4784e2fd10cc4fe5e38037d19ebf50d4ad7de6f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd</title>
<updated>2013-05-09T17:15:46Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-05-09T17:15:46Z</published>
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<id>urn:sha1:a637b0d45947df686979b85361ad5bfa9d19fdd3</id>
<content type='text'>
Pull MTD update from David Woodhouse:

 - Lots of cleanups from Artem, including deletion of some obsolete
   drivers

 - Support partitions larger than 4GiB in device tree

 - Support for new SPI chips

* tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd: (83 commits)
  mtd: omap2: Use module_platform_driver()
  mtd: bf5xx_nand: Use module_platform_driver()
  mtd: denali_dt: Remove redundant use of of_match_ptr
  mtd: denali_dt: Change return value to fix smatch warning
  mtd: denali_dt: Use module_platform_driver()
  mtd: denali_dt: Fix incorrect error check
  mtd: nand: subpage write support for hardware based ECC schemes
  mtd: omap2: use msecs_to_jiffies()
  mtd: nand_ids: use size macros
  mtd: nand_ids: improve LEGACY_ID_NAND macro a bit
  mtd: add 4 Toshiba nand chips for the full-id case
  mtd: add the support to parse out the full-id nand type
  mtd: add new fields to nand_flash_dev{}
  mtd: sh_flctl: Use of_match_ptr() macro
  mtd: gpio: Use of_match_ptr() macro
  mtd: gpio: Use devm_kzalloc()
  mtd: davinci_nand: Use of_match_ptr()
  mtd: dataflash: Use of_match_ptr() macro
  mtd: remove h720x flash support
  mtd: onenand: remove OneNAND simulator
  ...
</content>
</entry>
<entry>
<title>mtd_blktrans_ops-&gt;release() should return void</title>
<updated>2013-05-06T01:31:22Z</updated>
<author>
<name>Al Viro</name>
<email>viro@zeniv.linux.org.uk</email>
</author>
<published>2013-05-06T01:31:22Z</published>
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<id>urn:sha1:a8ca889ed9585894d53fd8919d80cbe8baff09e7</id>
<content type='text'>
Both existing instances always return 0 and even if they didn't,
the value would be lost on the way out.  Just don't bother...

Signed-off-by: Al Viro &lt;viro@zeniv.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>mtd: nand: subpage write support for hardware based ECC schemes</title>
<updated>2013-04-05T12:22:59Z</updated>
<author>
<name>Gupta, Pekon</name>
<email>pekon@ti.com</email>
</author>
<published>2013-03-15T12:25:53Z</published>
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<id>urn:sha1:837a6ba4f3b6d23026674e6af6b6849a4634fff9</id>
<content type='text'>
This patch adds support for subpage (partial-page) writes when using
hardware based ECC schemes.
Advantages:
(1) reduces storage overhead when using file-systems like UBIFS, which
store LEB header at page-size granularity.
(2) allows independent subpage writes, thereby increasing NAND storage
efficiency for non-page aligned data.
+ updated cafe_nand and lpc32xx_mlc NAND drivers for change in
chip-&gt;write_page interface.

Signed-off-by: Gupta, Pekon &lt;pekon@ti.com&gt;
Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand_ids: improve LEGACY_ID_NAND macro a bit</title>
<updated>2013-04-05T12:21:41Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-19T08:29:26Z</published>
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<id>urn:sha1:5bfa9b71a2d6642506e2dfdf49a66620f54f1d92</id>
<content type='text'>
Notice that all the flashes belonging to the "legacy ID" class have 512 bytes
NAND page. This means we may simplify the 'LEGACY_ID_NAND()' macro as well as
the NAND ID table a little.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: add new fields to nand_flash_dev{}</title>
<updated>2013-04-05T12:20:29Z</updated>
<author>
<name>Huang Shijie</name>
<email>b32955@freescale.com</email>
</author>
<published>2013-03-15T03:00:59Z</published>
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<id>urn:sha1:f22d5f638b0ea40e7cceb4639a608bd2c3eff97c</id>
<content type='text'>
As time goes on, we begin to meet the situation that we can not get enough
information from some nand chips's id data. Take some Toshiba's nand chips
for example. I have 4 Toshiba's nand chips in my hand:
	TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2, TC58NVG6D2

When we read these chips' datasheets, we will get the geometry of these chips:
	TC58NVG2S0F : 4096 + 224
	TC58NVG3S0F : 4096 + 232
	TC58NVG5D2  : 8192 + 640
	TC58NVG6D2  : 8192 + 640

But we can not parse out the correct oob size for these chips from the id data.

This patch adds some new fields to the nand_flash_dev{}:
  @id_len: the valid length of the id data. See the comments in
           nand_id_has_period()
  @oobsize: the oob size.

Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
Reviewed-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: introduce a macro for max NAND ID sequence length</title>
<updated>2013-04-05T12:15:06Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-14T07:57:23Z</published>
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<id>urn:sha1:53552d22bfe1f83f69f18eddae2f1d96249440f3</id>
<content type='text'>
Introduce a helpful macro for the maximum NAND ID sequence length instead of
using the "8" magic number.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Acked-by: Huang Shijie &lt;shijie8@gmail.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: use more reasonable integer types</title>
<updated>2013-04-05T12:15:00Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-13T11:45:00Z</published>
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<id>urn:sha1:ecb42fea59cf2d1e7160c5c7e707120e0e6714db</id>
<content type='text'>
Use 'unsigned int' instead of 'unsigned long' in the NAND chip description data
structure, because 32-bits is more than enough for our purposes. We do not need
64-bits, which is what we end up on 64-bit architectures. We declare many
instances of this data structure, so this should help saving some amount of
memory.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: physmap: add const qualifiers</title>
<updated>2013-04-05T12:02:40Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-12T08:32:52Z</published>
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<id>urn:sha1:f39cf6c7d472349a9907955ef213db1f26618ba0</id>
<content type='text'>
Be a bit stricter and add few more 'const' qualifiers.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: plat-ram: add const quilifiers</title>
<updated>2013-04-05T12:02:33Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-12T08:28:31Z</published>
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<id>urn:sha1:d50dcb1d0e1f8ebe11db1719aad5753cd1b4c4f8</id>
<content type='text'>
Be a bit stricter and add few more 'const' qualifiers.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
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