diff options
| author |   mguyler-ni <mark.guyler@ni.com> | 2019-02-26 17:43:34 -0800 |
|---|---|---|
| committer |   Brent Stapleton <brent.stapleton@ettus.com> | 2019-02-28 18:54:54 -0800 |
| commit | 98d2572a3fcd943e64a83b53e23ac01593bc359e (patch) | |
| tree | f2376e755b7656f9921e8b1a38b5cd498532b8c4 | |
| parent | x300: device args: Removed invalid 200 MHz sysref rate (diff) | |
| download | uhd-98d2572a3fcd943e64a83b53e23ac01593bc359e.tar.xz uhd-98d2572a3fcd943e64a83b53e23ac01593bc359e.zip | |
x300: Change PLL CP currents in x300_clock_ctrl
- modify PLL charge pump values to improve phase coherence
- affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a867a9138..9b54b001b 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -699,13 +699,13 @@ private: // PLL1 - 2 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 48; _lmk04816_regs.PLL1_R_27 = 5; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_4KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -722,13 +722,13 @@ private: // PLL1 - 1.92 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 6; _lmk04816_regs.PLL1_R_27 = 6; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -745,13 +745,13 @@ private: // PLL1 - 1.92 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 12; _lmk04816_regs.PLL1_R_27 = 12; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -768,13 +768,13 @@ private: // PLL1 - 2.048 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 15; _lmk04816_regs.PLL1_R_27 = 15; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; |