From 2e0db35eaf69947c344f67c9f38132e33f88a141 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 6 Mar 2024 11:28:05 -0600 Subject: fpga: Add Vivado project option to USRP FPGA builds --- fpga/usrp3/top/e31x/Makefile | 1 + fpga/usrp3/top/e320/Makefile | 1 + fpga/usrp3/top/n3xx/Makefile | 1 + fpga/usrp3/top/x300/Makefile | 1 + fpga/usrp3/top/x400/Makefile | 1 + 5 files changed, 5 insertions(+) diff --git a/fpga/usrp3/top/e31x/Makefile b/fpga/usrp3/top/e31x/Makefile index 8c0e32b56..83257a353 100644 --- a/fpga/usrp3/top/e31x/Makefile +++ b/fpga/usrp3/top/e31x/Makefile @@ -112,6 +112,7 @@ help: ##Show this help message. ##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build. ## Note: The RFNoC image core must also be configured to use DRAM. ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile index e2e6e8a79..cf22938ad 100644 --- a/fpga/usrp3/top/e320/Makefile +++ b/fpga/usrp3/top/e320/Makefile @@ -104,6 +104,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile index 5abafb3cd..62b85c3c1 100644 --- a/fpga/usrp3/top/n3xx/Makefile +++ b/fpga/usrp3/top/n3xx/Makefile @@ -207,6 +207,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile index 5c08fc1e1..3d974a84e 100644 --- a/fpga/usrp3/top/x300/Makefile +++ b/fpga/usrp3/top/x300/Makefile @@ -153,6 +153,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index a42c7b05d..1bf0d3fcd 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -331,6 +331,7 @@ help: ##Show this help message. ##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs ##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build. ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) -- cgit v1.2.3-59-g8ed1b