From 4b63ca00894944e03e7897f96316ab24cd5411d1 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 14 Mar 2024 11:44:56 -0500 Subject: fpga: Add incremental to strategies for e3xx, n3xx, x3xx --- fpga/usrp3/top/e31x/build_e31x.tcl | 5 ++++- fpga/usrp3/top/e320/build_e320.tcl | 5 ++++- fpga/usrp3/top/n3xx/build_n3xx.tcl | 5 ++++- fpga/usrp3/top/x300/build_x300.tcl | 7 +++++-- 4 files changed, 17 insertions(+), 5 deletions(-) diff --git a/fpga/usrp3/top/e31x/build_e31x.tcl b/fpga/usrp3/top/e31x/build_e31x.tcl index e07b124c2..3f1f0ff5c 100644 --- a/fpga/usrp3/top/e31x/build_e31x.tcl +++ b/fpga/usrp3/top/e31x/build_e31x.tcl @@ -1,5 +1,7 @@ # -# Copyright 2016 Ettus Research +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later # source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl @@ -14,6 +16,7 @@ vivado_utils::generate_post_synth_reports # STEP#3: Run implementation strategy set e31x_strategy [dict create] +dict set e31x_strategy "implementation.incremental" 0 dict set e31x_strategy "opt_design.is_enabled" 1 dict set e31x_strategy "opt_design.directive" "Default" dict set e31x_strategy "post_opt_power_opt_design.is_enabled" 0 diff --git a/fpga/usrp3/top/e320/build_e320.tcl b/fpga/usrp3/top/e320/build_e320.tcl index 757195865..a952e5f53 100644 --- a/fpga/usrp3/top/e320/build_e320.tcl +++ b/fpga/usrp3/top/e320/build_e320.tcl @@ -1,5 +1,7 @@ # -# Copyright 2016 Ettus Research +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later # source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl @@ -14,6 +16,7 @@ vivado_utils::generate_post_synth_reports # STEP#3: Run implementation strategy set e3xx_strategy [dict create] +dict set e3xx_strategy "implementation.incremental" 0 dict set e3xx_strategy "opt_design.is_enabled" 1 dict set e3xx_strategy "opt_design.directive" "Default" dict set e3xx_strategy "post_opt_power_opt_design.is_enabled" 0 diff --git a/fpga/usrp3/top/n3xx/build_n3xx.tcl b/fpga/usrp3/top/n3xx/build_n3xx.tcl index 45ba102c3..8946fd945 100644 --- a/fpga/usrp3/top/n3xx/build_n3xx.tcl +++ b/fpga/usrp3/top/n3xx/build_n3xx.tcl @@ -1,5 +1,7 @@ # -# Copyright 2016 Ettus Research +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later # source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl @@ -14,6 +16,7 @@ vivado_utils::generate_post_synth_reports # STEP#3: Run implementation strategy set n3xx_strategy [dict create] +dict set n3xx_strategy "implementation.incremental" 0 dict set n3xx_strategy "opt_design.is_enabled" 1 dict set n3xx_strategy "opt_design.directive" "NoBramPowerOpt" dict set n3xx_strategy "post_opt_power_opt_design.is_enabled" 0 diff --git a/fpga/usrp3/top/x300/build_x300.tcl b/fpga/usrp3/top/x300/build_x300.tcl index 87517e3b8..5a445423b 100644 --- a/fpga/usrp3/top/x300/build_x300.tcl +++ b/fpga/usrp3/top/x300/build_x300.tcl @@ -1,5 +1,7 @@ # -# Copyright 2014-2015 Ettus Research +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later # source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl @@ -8,12 +10,13 @@ source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl # STEP#1: Create project, add sources, refresh IP vivado_utils::initialize_project -# STEP#2: Run synthesis +# STEP#2: Run synthesis vivado_utils::synthesize_design vivado_utils::generate_post_synth_reports # STEP#3: Run implementation strategy set x3xx_strategy [dict create] +dict set x3xx_strategy "implementation.incremental" 0 dict set x3xx_strategy "opt_design.is_enabled" 1 dict set x3xx_strategy "opt_design.directive" "NoBramPowerOpt" dict set x3xx_strategy "post_opt_power_opt_design.is_enabled" 0 -- cgit v1.2.3-59-g8ed1b