wireguard-linux/Documentation/devicetree/bindings/display/msm, branch jd/unified-crypt-queue

dt-bindings: display: msm: Convert GMU bindings to YAML

2020-03-20T14:13:05Z

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings. The 'sram' text from the old binding never applied to the GMU so it was not converted but all the other properties were correct. Acked-by: Sam Ravnborg Reviewed-by: Rob Herring Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark

dt-bindings: display: msm: gmu: move sram property to gpu bindings

2020-03-19T19:23:31Z

The sram property was incorrectly added to the GMU binding when it really belongs with the GPU binding instead. Let's go ahead and move it. While changes are being made here, let's update the sram property description to mention that this property is only valid for a3xx and a4xx GPUs. The a3xx/a4xx example in the GPU is replaced with what was in the GMU. Signed-off-by: Brian Masney Fixes: 198a72c8f9ee ("dt-bindings: display: msm: gmu: add optional ocmem property") Acked-by: Jordan Crouse Signed-off-by: Rob Clark

dt-bindings: drm/msm/gpu: Document firmware-name

2020-01-13T20:45:42Z

The firmware-name property in the zap node can be used to specify a device specific zap firmware. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson

dt-bindings: msm:disp: add sc7180 DPU variant

2020-01-02T23:28:46Z

Add a compatible string to support sc7180 dpu version. Signed-off-by: Kalyan Thota Acked-by: Rob Herring Signed-off-by: Rob Clark

dt-bindings: drm/msm/gpu: document second interconnect

2020-01-02T22:20:42Z

Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Let's document this second interconnect path that's available. Since there's now two available interconnects, let's add the interconnect-names property. Signed-off-by: Brian Masney Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Rob Clark

dt-bindings: msm/mdp5: Document optional TBU and TBU_RT clocks

2019-11-04T21:17:27Z

These two clocks aren't present in all versions of the MDP5 HW: where present, they are needed to enable the Translation Buffer Unit(s). Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Signed-off-by: Rob Clark

dt-bindings: display: msm: gmu: add optional ocmem property

2019-10-07T15:10:37Z

Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. Add the optional ocmem property to the Adreno Graphics Management Unit bindings. Signed-off-by: Brian Masney Reviewed-by: Rob Herring Signed-off-by: Rob Clark

dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845

2019-06-20T15:39:24Z

Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Changes in v2: - None Changes in v3: - Remove common property definitions (Rob Herring) Changes in v4: - Use port macros and change port string names (Georgi Djakov) Changes in v5-v7: - None Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Jayant Shekhar Reviewed-by: Rob Herring Signed-off-by: Rob Clark

dt-bindings: msm/dsi: Add 10nm phy for msm8998 compatible

2019-06-18T20:56:42Z

The DSI phy on MSM8998 is a 10nm design like SDM845, however it has some slightly different quirks which need to be handled by drivers. Provide a separate compatible to assist in handling the specifics. Signed-off-by: Jeffrey Hugo Signed-off-by: Rob Clark

dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region

2019-04-21T14:37:17Z

Describe the zap-shader node that defines a reserved memory region to store the zap shader. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark