wireguard-linux/Documentation/devicetree/bindings/interconnect, branch stable

Merge tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

2026-08-25T16:38:50Z

Pull char/misc/IIO/etc driver updates from Greg KH: "Here is the big set of char, misc, iio, counter, fpga, and other small driver subsystems for 7.3-rc1. Overall, due to some driver removals we only added a bit more code than removed, which was a nice change. Highlights in this merge request are: - Loads of IIO driver updates and additions - binder driver updates (more on that below...) - Removal of the SGI XP and GRU drivers as they are not used anymore and turn out to be pretty insecure overall - Removal of the obsolete ibmasm driver as it's not being used anymore - Coresight driver updates and additions - Mei driver udpates - Counter driver updates - FPGA driver updates - ICC driver updates - lots and lots of other tiny driver updates to resolve reported issues All of these have been in linux-next for a while" * tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (513 commits) iio: chemical: atlas-sensor: use iio_trigger_poll_nested() to fix remove UAF iio: adc: pac1921: fix wrong channel used in trigger handler read iio: light: gp2ap002: re-enable irq if runtime suspend fails iio: light: gp2ap002: Fix unbalanced runtime PM on repeated event writes iio: light: apds9306: fix PM reference leak in apds9306_read_data() iio: gyro: mpu3050: fix sign of raw angular velocity readings iio: srf04: fix pm_runtime handling on probe error path iio: adc: ad4080: configure backend data size iio: adc: adi-axi-adc: add data size support for AD408X backend iio: chemical: atlas-sensor: fix PM reference leak in buffer postenable iio: dac: ad5446: fix OF module device table iio: light: opt4001: Fix reversed GENMASK() arguments in fault count mask iio: light: opt4001: Reject integration times with a non-zero seconds part iio: light: opt4001: Fix incompatible pointer type passed to div_u64_rem() iio: light: opt4001: Fix power down clearing bits of the wrong register iio: light: opt4060: Fix incorrect register name in threshold read error message iio: light: opt4060: Fix pointer type passed to div_u64_rem() iio: light: opt4060: Reject integration times with a non-zero seconds part iio: light: ltrf216a: fix runtime PM reference leak in error path iio: pressure: dps310: fix NULL pointer dereference on ACPI probe ...

dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible

2026-08-15T20:46:52Z

Add the Qualcomm Maili SoC compatible string for the CPU bandwidth monitor (BWMONv4). This falls back to the sdm845-bwmon compatible, consistent with the existing pattern used by other recent SoCs such as sm8750 and kaanapali. Signed-off-by: Yijie Yang Acked-by: Krzysztof Kozlowski Reviewed-by: Jingyi Wang Link: https://patch.msgid.link/20260811-bwmon-v2-1-80f7f150ab9e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm)

Merge branch 'icc-maili' into icc-next

2026-07-22T10:51:09Z

Add interconnect bindings and RPMh-based interconnect driver support for the upcoming Qualcomm Maili SoC. * icc-maili dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC interconnect: qcom: add Maili interconnect provider driver Link: https://patch.msgid.link/20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-shikra' into icc-next

2026-07-22T10:50:47Z

Add Epoch Subsystem (EPSS) L3 scaling support on Qualcomm Shikra SoC. EPSS hardware on Shikra is similar to other SoCs but supports only twelve L3 frequency entries (LUT). Reading the LUT beyond supported frequencies can expose incorrect frequencies. Introduce new compatible to represent this constrained variant of EPSS. * icc-shikra dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-0-3c2e0b796e78@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible

2026-07-14T22:48:51Z

Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR bandwidth monitor. Shikra has a BWMONv5 for CPU. Signed-off-by: Sayantan Chakraborty Acked-by: Krzysztof Kozlowski Signed-off-by: Komal Bajaj Link: https://patch.msgid.link/20260714-shikra-dt-m1-v6-1-bee265d3499b@oss.qualcomm.com Signed-off-by: Rob Herring (Arm)

dt-bindings: interconnect: qcom-bwmon: Document Eliza BWMONs compatible

2026-07-14T22:27:06Z

Document Eliza BWMONs which has a BWMONv4 for CPU-LLCC and a BWMONv5 for DDR-LLCC paths, same as SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260708-bindings-llcc-bwmon-eliza-v1-1-3c7dbcbae87a@oss.qualcomm.com Signed-off-by: Rob Herring (Arm)

dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC

2026-07-07T14:17:44Z

Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili SoC. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260622-maili_icc-v2-1-18b5ac08c04f@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC

2026-07-07T14:06:40Z

Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-1-3c2e0b796e78@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-x1e80100' into icc-next

2026-07-07T13:32:56Z

This series enables QoS configuration for QNOC type device which can be found on X1E80100 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-x1e80100 dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS interconnect: qcom: x1e80100: enable QoS configuration Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS

2026-07-07T13:32:00Z

Some interconnect nodes on X1E80100 have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock-gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-1-305c6539e6d2@oss.qualcomm.com Signed-off-by: Georgi Djakov