wireguard-linux/Documentation/devicetree/bindings/mailbox, branch jd/bump-compilers

dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings

2024-07-10T18:24:55Z

Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox controller. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Jassi Brar

dt-bindings: mailbox: Add mediatek,gce-props.yaml

2024-07-10T18:24:55Z

Add mediatek,gce-props.yaml for common GCE properties that is used for both mailbox providers and consumers. We place the common property "mediatek,gce-events" in this binding currently. The property "mediatek,gce-events" is used for GCE event ID corresponding to a hardware event signal sent by the hardware or a software driver. If the mailbox providers or consumers want to manipulate the value of the event ID, they need to know the specific event ID. Signed-off-by: Jason-JH.Lin Reviewed-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jassi Brar

dt-bindings: mailbox: qcom-ipcc: Document the SDX75 IPCC

2024-05-20T03:33:58Z

Document the Inter-Processor Communication Controller on the SDX75 Platform. Signed-off-by: Rohit Agarwal Acked-by: Rob Herring (Arm) Signed-off-by: Jassi Brar

dt-bindings: mailbox: qcom: Add MSM8974 APCS compatible

2024-05-20T03:33:51Z

Add compatible for the Qualcomm MSM8974 APCS block. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jassi Brar

dt-bindings: mailbox: arm,mhuv3: Add bindings

2024-05-20T03:30:09Z

Add bindings for the ARM MHUv3 Mailbox controller. Reviewed-by: Rob Herring Signed-off-by: Cristian Marussi Signed-off-by: Jassi Brar

dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible

2024-03-11T00:05:23Z

Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string. And the MUs in AONMIX has internal RAMs for SCMI shared buffer usage. Reviewed-by: Conor Dooley Signed-off-by: Peng Fan Signed-off-by: Jassi Brar

dt-bindings: mailbox: qcom-ipcc: document the X1E80100 Inter-Processor Communication Controller

2024-01-14T05:08:51Z

Document the Inter-Processor Communication Controller on the X1E80100 Platform. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar

dt-bindings: mailbox: add Versal IPI bindings

2024-01-14T05:08:50Z

Add documentation for AMD-Xilinx Versal platform Inter Processor Interrupt controller. Versal IPI controller contains buffer-less IPI which do not have buffers for message passing. For such IPI channels message buffers are not expected and only notification to/from remote agent is expected. Signed-off-by: Tanmay Shah Acked-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar

dt-bindings: mailbox: zynqmp: extend required list

2024-01-14T05:08:50Z

"xlnx,ipi-id" is handled as required property but is missing from binding doc required list of mailbox child node. Add that to required list. This does not break backward compatibility but bug in bindings document. Fixes: 4a855a957936 ("dt-bindings: mailbox: zynqmp_ipi: convert to yaml") Signed-off-by: Tanmay Shah Acked-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar

dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks

2024-01-14T05:08:50Z

Rework the compatibles and group devices which have similar interface (same from Linux driver point of view) as compatible. This allows smaller of_device_id table in the Linux driver and smaller allOf:if:then: constraints. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Jassi Brar