<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/Documentation/devicetree/bindings/pci, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/pci?h=jd%2Funified-crypt-queue</id>
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<updated>2020-04-03T22:22:05Z</updated>
<entry>
<title>Merge tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2020-04-03T22:22:05Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-04-03T22:22:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=854e80bcfdafb8d99d308e21798cd0116338783d'/>
<id>urn:sha1:854e80bcfdafb8d99d308e21798cd0116338783d</id>
<content type='text'>
Pull ARM devicetree updates from Arnd Bergmann:
 "Most of the commits are for additional hardware support and minor
  fixes for existing machines for all the usual platforms: qcom,
  amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape,
  uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas,
  sunxi, broadcom, omap, and versatile.

  The conversion of binding files to machine-readable yaml format
  continues, along with fixes found during the validation. Andre
  Przywara takes over maintainership for the old Calxeda Highbank
  platform and provides a number of updates.

  The OMAP2+ platforms see a continued move from platform data into dts
  files, for many devices that relied on a mix of auxiliary data in
  addition to the DT description

  A moderate number of new SoCs and machines are added, here is a full
  list:

   - Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865
     (SM8250) is the current high-end phone chip, and IPQ6018 is a new
     WiFi-6 router chip.

   - Mediatek MT8516 application processor SoC for voice assistants,
     along with the "pumpkin" development board

   - NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an
     evaluation board.

   - Kontron "sl28" board family based on NXP LS1028A

   - Eleven variations of the new i.MX6 TechNexion Pico board, combining
     the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7
     SoM carriers

   - Three additional variants of the Toradex Colibri board family, all
     based on versions of the NXP i.MX7.

   - The Pinebook Pro laptop based on Rockchip RK3399

   - Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based
     on the ST-Ericsson u8500 platform

   - DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on
     STMicroelectronics stm32mp157

   - Renesas M3ULCB starter kit for R-Car M3-W+

   - Hoperun HiHope development board with Renesas RZ/G2M

   - Pine64 PineTab tablet and PinePhone phone, both based on Allwinner
     A64

   - Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner
     A20

   - PocketBook Touch Lux 3 ebook reader, based on Allwinner A13"

* tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits)
  ARM: dts: ux500: Fix missing node renames
  arm64: dts: Revert "specify console via command line"
  MAINTAINERS: Update Calxeda Highbank maintainership
  arm: dts: calxeda: Group port-phys and sgpio-gpio items
  arm: dts: calxeda: Fix interrupt grouping
  arm: dts: calxeda: Provide UART clock
  arm: dts: calxeda: Basic DT file fixes
  arm64: dts: specify console via command line
  ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node
  ARM: dts: gemini: Add thermal zone to DIR-685
  ARM: dts: gemini: Rename IDE nodes
  ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes
  arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
  arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
  arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
  arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
  arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
  arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes
  arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
  arm64: dts: khadas-vim3: add SPIFC controller node
  ...
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/mobiveil'</title>
<updated>2020-04-02T19:27:01Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-04-02T19:27:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d09fca9ecddb675d0c52499a729a687a22a77443'/>
<id>urn:sha1:d09fca9ecddb675d0c52499a729a687a22a77443</id>
<content type='text'>
  - Restructure mobiveil driver to support either Root Complex mode or
    Endpoint mode (Hou Zhiqiang)

  - Collect host initialization into one place (Hou Zhiqiang)

  - Collect interrupt-related code into one place (Hou Zhiqiang)

  - Split mobiveil into separate files under
    drivers/pci/controller/mobiveil for easier reuse (Hou Zhiqiang)

  - Add callbacks for interrupt initialization and linkup checking (Hou
    Zhiqiang)

  - Add 8- and 16-bit CSR accessors (Hou Zhiqiang)

  - Initialize host driver only if Header Type is "bridge" (Hou Zhiqiang)

  - Add DT bindings for NXP Layerscape SoCs PCIe Gen4 controller (Hou
    Zhiqiang)

  - Add PCIe Gen4 RC driver for Layerscape SoCs (Hou Zhiqiang)

  - Add pcie-mobiveil __iomem annotations (Hou Zhiqiang)

  - Add PCI_MSI_IRQ_DOMAIN Kconfig dependency (Hou Zhiqiang)

* remotes/lorenzo/pci/mobiveil:
  PCI: mobiveil: Fix unmet dependency warning for PCIE_MOBIVEIL_PLAT
  PCI: mobiveil: Fix sparse different address space warnings
  PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs
  dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller
  PCI: mobiveil: Add Header Type field check
  PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
  PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host
  PCI: mobiveil: Add callback function for link up check
  PCI: mobiveil: Add callback function for interrupt initialization
  PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver
  PCI: mobiveil: Collect the interrupt related operations into a function
  PCI: mobiveil: Move the host initialization into a function
  PCI: mobiveil: Introduce a new structure mobiveil_root_port
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/endpoint'</title>
<updated>2020-04-02T19:26:57Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-04-02T19:26:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b16f2ab280f9c172ea02286fa298d5c8a3d68c88'/>
<id>urn:sha1:b16f2ab280f9c172ea02286fa298d5c8a3d68c88</id>
<content type='text'>
  - Use notification chain instead of EPF linkup ops for EPC events (Kishon
    Vijay Abraham I)

  - Protect concurrent allocation in endpoint outbound address region
    (Kishon Vijay Abraham I)

  - Protect concurrent access to pci_epf_ops (Kishon Vijay Abraham I)

  - Assign function number for each PF in endpoint core (Kishon Vijay
    Abraham I)

  - Refactor endpoint mode core initialization (Vidya Sagar)

  - Add API to notify when core initialization completes (Vidya Sagar)

  - Add test framework support to defer core initialization (Vidya Sagar)

  - Update Tegra SoC ABI header to support uninitialization of UPHY PLL
    when in endpoint mode without reference clock (Vidya Sagar)

  - Add DT and driver support for Tegra194 PCIe endpoint nodes (Vidya
    Sagar)

  - Add endpoint test support for DMA data transfer (Kishon Vijay
    Abraham I)

  - Print throughput information in endpoint test (Kishon Vijay Abraham I)

  - Use streaming DMA APIs for endpoint test buffer allocation (Kishon
    Vijay Abraham I)

  - Add endpoint test command line option for DMA (Kishon Vijay Abraham I)

  - When stopping a controller via configfs, clear endpoint "start" entry
    to prevent WARN_ON (Kunihiko Hayashi)

  - Update endpoint -&gt;set_msix() to pay attention to MSI-X BAR Indicator
    and offset when finding MSI-X tables (Kishon Vijay Abraham I)

  - MSI-X tables are in local memory, not in the PCI address space.  Update
    pcie-designware-ep to account for this (Kishon Vijay Abraham I)

  - Allow AM654 PCIe Endpoint to raise MSI-X interrupts (Kishon Vijay
    Abraham I)

  - Avoid using module parameter to determine irqtype for endpoint test
    (Kishon Vijay Abraham I)

  - Add ioctl to clear IRQ for endpoint test (Kishon Vijay Abraham I)

  - Add endpoint test 'e' option to clear IRQ (Kishon Vijay Abraham I)

  - Bump limit on number of endpoint test devices from 10 to 10,000 (Kishon
    Vijay Abraham I)

  - Use full pci-endpoint-test name in request_irq() for easier profiling
    (Kishon Vijay Abraham I)

  - Reduce log level of -EPROBE_DEFER error messages to debug (Thierry
    Reding)

* remotes/lorenzo/pci/endpoint:
  misc: pci_endpoint_test: remove duplicate macro PCI_ENDPOINT_TEST_STATUS
  PCI: tegra: Print -EPROBE_DEFER error message at debug level
  misc: pci_endpoint_test: Use full pci-endpoint-test name in request_irq()
  misc: pci_endpoint_test: Fix to support &gt; 10 pci-endpoint-test devices
  tools: PCI: Add 'e' to clear IRQ
  misc: pci_endpoint_test: Add ioctl to clear IRQ
  misc: pci_endpoint_test: Avoid using module parameter to determine irqtype
  PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt
  PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
  PCI: endpoint: Fix -&gt;set_msix() to take BIR and offset as arguments
  misc: pci_endpoint_test: Add support to get DMA option from userspace
  tools: PCI: Add 'd' command line option to support DMA
  misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation
  PCI: endpoint: functions/pci-epf-test: Print throughput information
  PCI: endpoint: functions/pci-epf-test: Add DMA support to transfer data
  PCI: endpoint: Fix clearing start entry in configfs
  PCI: tegra: Add support for PCIe endpoint mode in Tegra194
  dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194
  soc/tegra: bpmp: Update ABI header
  PCI: pci-epf-test: Add support to defer core initialization
  PCI: dwc: Add API to notify core initialization completion
  PCI: endpoint: Add notification for core init completion
  PCI: dwc: Refactor core initialization code for EP mode
  PCI: endpoint: Add core init notifying feature
  PCI: endpoint: Assign function number for each PF in EPC core
  PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
  PCI: endpoint: Fix for concurrent memory allocation in OB address region
  PCI: endpoint: Replace spinlock with mutex
  PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/dt'</title>
<updated>2020-04-02T19:26:50Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-04-02T19:26:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=86d0b6a131052b6b98ebda5a65c03a9f89914316'/>
<id>urn:sha1:86d0b6a131052b6b98ebda5a65c03a9f89914316</id>
<content type='text'>
  - Add common schema for PCI endpoint controllers (Kishon Vijay Abraham I)

  - Add host and endpoint schemas for Cadence PCIe core (Kishon Vijay
    Abraham I)

  - Convert Cadence platform bindings to DT schema (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/dt:
  dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema
  dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
  dt-bindings: PCI: Add PCI Endpoint Controller Schema
</content>
</entry>
<entry>
<title>dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema</title>
<updated>2020-03-20T09:55:21Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-03-05T10:30:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=11be8af70d86c0a03706b329fb6f1a7329e3343a'/>
<id>urn:sha1:11be8af70d86c0a03706b329fb6f1a7329e3343a</id>
<content type='text'>
Include Cadence core DT schema and define the Cadence platform DT schema
for both Host and Endpoint mode. Note: The Cadence core DT schema could
be included for other platforms using Cadence PCIe core.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe</title>
<updated>2020-03-20T09:55:14Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-03-05T10:30:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=69501078fc605810d777a4bbc4df7d09c561998e'/>
<id>urn:sha1:69501078fc605810d777a4bbc4df7d09c561998e</id>
<content type='text'>
Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence
PCIe core library. Platforms using Cadence PCIe core can include the
schemas added here in the platform specific schemas.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: Add PCI Endpoint Controller Schema</title>
<updated>2020-03-20T09:55:02Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-03-05T10:30:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=847dbf4e1aba7e6fc3c19c22a046a34eba1cf76a'/>
<id>urn:sha1:847dbf4e1aba7e6fc3c19c22a046a34eba1cf76a</id>
<content type='text'>
Define a common schema for PCI Endpoint Controllers.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Fix Tegra194 PCIe compatible string</title>
<updated>2020-03-12T11:14:25Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2020-02-14T13:53:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f9f711efd441ad0d22874be49986d92121862335'/>
<id>urn:sha1:f9f711efd441ad0d22874be49986d92121862335</id>
<content type='text'>
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic
designware PCIe platform driver instead of the Tegra194 designware PCIe
driver. This causes a boot failure on Tegra194 because the necessary
configuration to access the hardware is not performed.

The order in which the compatible strings are populated in Device-Tree
is not relevant in this case, because the kernel will attempt to probe
the device as soon as a driver is loaded and if the generic designware
PCIe driver is loaded first, then this driver will be probed first.
Therefore, to fix this problem, remove the "snps,dw-pcie" string from
the compatible string as we never want this driver to be probe on
Tegra194.

Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194</title>
<updated>2020-03-11T10:20:35Z</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2020-03-03T18:10:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9f04d18b1edf1992e1dd606933839d725aec9b1f'/>
<id>urn:sha1:9f04d18b1edf1992e1dd606933839d725aec9b1f</id>
<content type='text'>
Add support for PCIe controllers that can operate in endpoint mode
in Tegra194.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: meson: Update PCIE bindings documentation</title>
<updated>2020-03-04T10:50:18Z</updated>
<author>
<name>Remi Pommarel</name>
<email>repk@triplefau.lt</email>
</author>
<published>2020-01-23T23:29:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6e5f77031cc92397aba2d03c9f82bfc511b83467'/>
<id>urn:sha1:6e5f77031cc92397aba2d03c9f82bfc511b83467</id>
<content type='text'>
Now that a new PHYs has been introduced for AXG SoC family, update
dt bindings documentation.

Please note that this breaks backward compatibility but as not a single
devicetree uses that yet that seems ok.

Signed-off-by: Remi Pommarel &lt;repk@triplefau.lt&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
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