<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/Documentation/devicetree/bindings/phy, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/phy?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/phy?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-10-15T16:51:18Z</updated>
<entry>
<title>Merge tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb</title>
<updated>2020-10-15T16:51:18Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-10-15T16:51:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c6dbef7307629cce855aa6b482b60cbf7777ed88'/>
<id>urn:sha1:c6dbef7307629cce855aa6b482b60cbf7777ed88</id>
<content type='text'>
Pull USB/PHY/Thunderbolt driver updates from Greg KH:
 "Here is the big set of USB, PHY, and Thunderbolt driver updates for
  5.10-rc1.

  Lots of tiny different things for these subsystems are in here,
  including:

   - phy driver updates

   - thunderbolt / USB 4 updates and additions

   - USB gadget driver updates

   - xhci fixes and updates

   - typec driver additions and updates

   - api conversions to various drivers for core kernel api changes

   - new USB control message functions to make it harder to get wrong,
     as found by syzbot (took 2 tries to get it right)

   - lots of tiny USB driver fixes and updates all over the place

  All of these have been in linux-next for a while, with the exception
  of the last "obviously correct" patch that updated a FALLTHROUGH
  comment that got merged last weekend"

* tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (374 commits)
  usb: musb: gadget: Use fallthrough pseudo-keyword
  usb: typec: Add QCOM PMIC typec detection driver
  USB: serial: option: add Cellient MPL200 card
  usb: typec: tcpci_maxim: Add support for Sink FRS
  usb: typec: tcpci: Implement callbacks for FRS
  usb: typec: tcpm: Add support for Sink Fast Role SWAP(FRS)
  usb: typec: tcpci_maxim: Chip level TCPC driver
  usb: typec: tcpci: Add set_vbus tcpci callback
  usb: typec: tcpci: Add a getter method to retrieve tcpm_port reference
  usbip: vhci_hcd: fix calling usb_hcd_giveback_urb() with irqs enabled
  usb: cdc-acm: add quirk to blacklist ETAS ES58X devices
  USB: serial: ftdi_sio: use cur_altsetting for consistency
  USB: serial: option: Add Telit FT980-KS composition
  USB: core: remove polling for /sys/kernel/debug/usb/devices
  usb: typec: add support for STUSB160x Type-C controller family
  usb: typec: add typec_find_pwr_opmode
  usb: typec: hd3ss3220: Use OF graph API to get the connector fwnode
  dt-bindings: usb: renesas,usb3-peri: Document HS and SS data bus
  dt-bindings: usb: convert ti,hd3ss3220 bindings to json-schema
  usb: dwc2: Fix INTR OUT transfers in DDMA mode.
  ...
</content>
</entry>
<entry>
<title>dt-bindings: Another round of adding missing 'additionalProperties'</title>
<updated>2020-10-06T15:55:25Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2020-10-02T23:41:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5be478f9c24fbdf8162b8118b8da8cc685e2efb4'/>
<id>urn:sha1:5be478f9c24fbdf8162b8118b8da8cc685e2efb4</id>
<content type='text'>
Another round of wack-a-mole. The json-schema default is additional
unknown properties are allowed, but for DT all properties should be
defined.

Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Stephen Boyd &lt;sboyd@kernel.org&gt;
Cc: Shawn Guo &lt;shawnguo@kernel.org&gt;
Cc: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Cc: Baolin Wang &lt;baolin.wang7@gmail.com&gt;
Cc: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
Cc: Laurent Pinchart &lt;laurent.pinchart+renesas@ideasonboard.com&gt;
Cc: "David S. Miller" &lt;davem@davemloft.net&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Liam Girdwood &lt;lgirdwood@gmail.com&gt;
Cc: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Reviewed-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Acked-By: Vinod Koul &lt;vkoul@kernel.org&gt;
Acked-by: Lee Jones &lt;lee.jones@linaro.org&gt;
Acked-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Acked-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt; # for iio
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Reviewd-by: Corey Minyard &lt;cminyard@mvista.com&gt;
Acked-by: Pavel Machek &lt;pavel@ucw.cz&gt;
Acked-by: Sebastian Reichel &lt;sre@kernel.org&gt;
Link: https://lore.kernel.org/r/20201002234143.3570746-1-robh@kernel.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information</title>
<updated>2020-09-28T05:57:53Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2020-09-16T23:11:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=724fabf5df1342eae363fd3bfc091b5d160225d3'/>
<id>urn:sha1:724fabf5df1342eae363fd3bfc091b5d160225d3</id>
<content type='text'>
This binding only describes the USB phy inside the USB3 + DP "combo"
phy. Add information for the DP phy and describe the sub-nodes that
represent the DP and USB3 phys that exist inside the combo wrapper.
Remove reg-names from required properties because it isn't required nor
used by the kernel driver.

Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Jeykumar Sankaran &lt;jsanka@codeaurora.org&gt;
Cc: Chandan Uddaraju &lt;chandanu@codeaurora.org&gt;
Cc: Vara Reddy &lt;varar@codeaurora.org&gt;
Cc: Tanmay Shah &lt;tanmay@codeaurora.org&gt;
Cc: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Cc: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Cc: Sandeep Maheswaram &lt;sanm@codeaurora.org&gt;
Cc: Douglas Anderson &lt;dianders@chromium.org&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Jonathan Marek &lt;jonathan@marek.ca&gt;
Cc: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Cc: &lt;devicetree@vger.kernel.org&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Rob Clark &lt;robdclark@chromium.org&gt;
Link: https://lore.kernel.org/r/20200916231202.3637932-2-swboyd@chromium.org
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy</title>
<updated>2020-09-23T05:27:51Z</updated>
<author>
<name>Tomi Valkeinen</name>
<email>tomi.valkeinen@ti.com</email>
</author>
<published>2020-09-18T08:37:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b7132285c65b52afd73139a8386184ff81c3fcb7'/>
<id>urn:sha1:b7132285c65b52afd73139a8386184ff81c3fcb7</id>
<content type='text'>
When WIZ wraps a Cadence Torrent PHY (instead of Cadence Sierra PHY)
there is a difference in the refclk-dig node: Torrent only has two
clocks instead of Sierra's four clocks. Add minItems: 2 to solve this.

Additionally, in our use case we only need to use assigned-clock for a
single clock, but the current binding requires either no assigned-clocks
or two. Fix this by adding minItems: 1 to all the assigned-clock
properties.

There was also an extra trailing whitespace, which this patch removes.

Signed-off-by: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Link: https://lore.kernel.org/r/20200918083743.213874-2-tomi.valkeinen@ti.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: cdns,torrent-phy: add reset-names</title>
<updated>2020-09-23T05:27:50Z</updated>
<author>
<name>Tomi Valkeinen</name>
<email>tomi.valkeinen@ti.com</email>
</author>
<published>2020-09-18T08:37:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4feac940ec142f70dd8600c5b73bef1cab5fde10'/>
<id>urn:sha1:4feac940ec142f70dd8600c5b73bef1cab5fde10</id>
<content type='text'>
Add reset-names as a required property.

There are no dts files using torrent phy yet, so it is safe to add a new
required property.

Signed-off-by: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Link: https://lore.kernel.org/r/20200918083743.213874-1-tomi.valkeinen@ti.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: cadence-torrent: Update Torrent PHY bindings for generic use</title>
<updated>2020-09-18T05:04:48Z</updated>
<author>
<name>Swapnil Jakhade</name>
<email>sjakhade@cadence.com</email>
</author>
<published>2020-09-16T18:28:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=074e991535942369b95ee5520a424e868cfaf8f7'/>
<id>urn:sha1:074e991535942369b95ee5520a424e868cfaf8f7</id>
<content type='text'>
Torrent PHY can be used in different multi-link multi-protocol
configurations including protocols other than DisplayPort also,
such as PCIe, USB, SGMII, QSGMII etc. Update the bindings to have
support for these configurations.

Signed-off-by: Swapnil Jakhade &lt;sjakhade@cadence.com&gt;
Link: https://lore.kernel.org/r/1600280911-9214-8-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: cadence-torrent: Add binding to specify SSC mode</title>
<updated>2020-09-18T05:04:48Z</updated>
<author>
<name>Swapnil Jakhade</name>
<email>sjakhade@cadence.com</email>
</author>
<published>2020-09-16T18:28:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=962fad301c33dec69324dc2d9320fd84a119a24c'/>
<id>urn:sha1:962fad301c33dec69324dc2d9320fd84a119a24c</id>
<content type='text'>
Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade &lt;sjakhade@cadence.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: intel: Add Keem Bay eMMC PHY bindings</title>
<updated>2020-09-16T12:15:19Z</updated>
<author>
<name>Wan Ahmad Zainie</name>
<email>wan.ahmad.zainie.wan.mohamad@intel.com</email>
</author>
<published>2020-09-13T23:55:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9580b22aca2c6996d4d2126cda0a610eb43165b9'/>
<id>urn:sha1:9580b22aca2c6996d4d2126cda0a610eb43165b9</id>
<content type='text'>
Binding description for Intel Keem Bay eMMC PHY.

Signed-off-by: Wan Ahmad Zainie &lt;wan.ahmad.zainie.wan.mohamad@intel.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20200913235522.4316-3-wan.ahmad.zainie.wan.mohamad@intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: convert phy-hi3660-usb3.txt to yaml</title>
<updated>2020-09-14T21:10:55Z</updated>
<author>
<name>Mauro Carvalho Chehab</name>
<email>mchehab+huawei@kernel.org</email>
</author>
<published>2020-09-04T07:58:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5ed5807364a59f3adef2b21f718864d601d167ca'/>
<id>urn:sha1:5ed5807364a59f3adef2b21f718864d601d167ca</id>
<content type='text'>
Convert Hisilicon Kirin 960 USB3 PHY bindings to DT schema
format using json-schema.

Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+huawei@kernel.org&gt;
Link: https://lore.kernel.org/r/edfeafe6b5a60a84d08095fb380f32e61af46d40.1599206213.git.mchehab+huawei@kernel.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: phy: Add USB PHY support for Intel LGM SoC</title>
<updated>2020-09-11T11:42:49Z</updated>
<author>
<name>Ramuthevar Vadivel Murugan</name>
<email>vadivel.muruganx.ramuthevar@linux.intel.com</email>
</author>
<published>2020-08-28T02:23:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8a676e1be4e0a41067808a2dba02127aee6fc277'/>
<id>urn:sha1:8a676e1be4e0a41067808a2dba02127aee6fc277</id>
<content type='text'>
Add the dt-schema to support USB PHY on Intel LGM SoC

Signed-off-by: Ramuthevar Vadivel Murugan &lt;vadivel.muruganx.ramuthevar@linux.intel.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20200828022312.52724-2-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
</feed>
