<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/Documentation/devicetree/bindings/pinctrl, branch jd/bump-compilers</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/pinctrl?h=jd%2Fbump-compilers</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/pinctrl?h=jd%2Fbump-compilers'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-07-29T19:35:47Z</updated>
<entry>
<title>dt-bindings: Batch-update Konrad Dybcio's email</title>
<updated>2024-07-29T19:35:47Z</updated>
<author>
<name>Konrad Dybcio</name>
<email>konrad.dybcio@linaro.org</email>
</author>
<published>2024-07-26T11:18:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0710c3d304f67f9b68f5082214e311ec8f82bd82'/>
<id>urn:sha1:0710c3d304f67f9b68f5082214e311ec8f82bd82</id>
<content type='text'>
Use my @kernel.org address everywhere.

Signed-off-by: Konrad Dybcio &lt;konradybcio@kernel.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20240726-topic-konrad_email-v1-3-f94665da2919@kernel.org
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2024-07-21T17:25:59Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-07-21T17:25:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8e313211f7d46d42b6aa7601b972fe89dcc4a076'/>
<id>urn:sha1:8e313211f7d46d42b6aa7601b972fe89dcc4a076</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "Some new drivers is the main part, the rest is cleanups and nonurgent
  fixes.

  Nothing much special about this, no core changes this time.

  New drivers:

   - Renesas RZ/V2H(P) SoC

   - NXP Freescale i.MX91 SoC

   - Nuvoton MA35D1 SoC

   - Qualcomm PMC8380, SM4250, SM4250 LPI

  Enhancements:

   - A slew of scoped-based simplifications of of_node_put()"

* tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
  pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
  pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
  pinctrl: renesas: rzg2l: Clarify OEN read/write support
  dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description
  dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function
  dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties
  pinctrl: freescale: Use scope based of_node_put() cleanups
  pinctrl: equilibrium: Use scope based of_node_put() cleanups
  pinctrl: ti: iodelay: Use scope based of_node_put() cleanups
  pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
  pinctrl: cy8c95x0: Update cache modification
  pinctrl: cy8c95x0: Use cleanup.h
  pinctrl: renesas: r8a779h0: Remove unneeded separators
  pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function
  pinctrl: renesas: r8a779g0: Remove unneeded separators
  pinctrl: renesas: r8a779h0: Add AVB MII pins and groups
  pinctrl: renesas: r8a779g0: Fix TPU suffixes
  pinctrl: renesas: r8a779g0: Fix TCLK suffixes
  pinctrl: renesas: r8a779g0: FIX PWM suffixes
  pinctrl: renesas: r8a779g0: Fix IRQ suffixes
  ...
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description</title>
<updated>2024-07-03T12:50:35Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2024-06-27T15:06:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=30b7748b2bc888ac1283a2715119b32d6d50cead'/>
<id>urn:sha1:30b7748b2bc888ac1283a2715119b32d6d50cead</id>
<content type='text'>
The binding is supposed to describe the properties of each element
of the pinctrl-single,gpio-range array entry, however when we use
"- items:" instead of "items:", it explicitly describes that there
is just a single entry in the array.

The pinctrl-single,gpio-range property should describe more than one
entry in the array. Fix the typo and adjust the alignment of the
description of the entries appropriately.

Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml")
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/20240627150610.469645-1-nm@ti.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function</title>
<updated>2024-07-03T12:49:36Z</updated>
<author>
<name>Tomer Maimon</name>
<email>tmaimon77@gmail.com</email>
</author>
<published>2024-06-30T09:01:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1024f5356715aa0699361a08e9dc1e5f798c8ae7'/>
<id>urn:sha1:1024f5356715aa0699361a08e9dc1e5f798c8ae7</id>
<content type='text'>
Add the following missing pin group and mux function:
smb6b, smb6c, smb6d, smb7b, smb7c, smb7d, bu4, bu4b, bu5, bu5b, bu6,
gpo187.

Signed-off-by: Tomer Maimon &lt;tmaimon77@gmail.com&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/20240630090104.565779-1-tmaimon77@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties</title>
<updated>2024-07-03T12:45:43Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2024-06-19T23:14:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=78d8815031fb6542c81f4625376489a99e208d47'/>
<id>urn:sha1:78d8815031fb6542c81f4625376489a99e208d47</id>
<content type='text'>
The "pinctrl-single,input-schmitt" have four arguments in the bindings
but the driver needs two. According to the meaning of other properties
and driver, it should have "enable" suffix. Fortunately, there is no
dts using this property, so it is safe to correct this property with the
right name.

Rename existed property "pinctrl-single,input-schmitt" to
"pinctrl-single,input-schmitt-enable" and add the right description for
property "pinctrl-single,input-schmitt" used by the driver.

Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/IA1PR20MB4953D5E7D7D68DDCE31C0031BBCF2@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: aspeed,ast2600-pinctrl: add NCSI groups</title>
<updated>2024-06-26T10:41:07Z</updated>
<author>
<name>Potin Lai</name>
<email>potin.lai.pt@gmail.com</email>
</author>
<published>2024-06-21T09:31:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=49b2b5c39e10fd442b89844ae6a510a207c0c8c9'/>
<id>urn:sha1:49b2b5c39e10fd442b89844ae6a510a207c0c8c9</id>
<content type='text'>
In the NCSI pin table, the reference clock output pin (RMIIXRCLKO) is not
needed on the management controller side.

Add "NCSI" pin groups that are equivalent to the RMII pin groups, but
without the RMIIXRCLKO pin.

Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Potin Lai &lt;potin.lai.pt@gmail.com&gt;
Reviewed-by: Andrew Jeffery &lt;andrew@codeconstruct.com.au&gt;
Link: https://lore.kernel.org/20240621093142.698529-2-potin.lai.pt@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: qcom: Add SM4250 pinctrl</title>
<updated>2024-06-26T10:41:07Z</updated>
<author>
<name>Srinivas Kandagatla</name>
<email>srinivas.kandagatla@linaro.org</email>
</author>
<published>2024-06-22T16:49:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2ffa7a35466212f31a0ffda5d948c49a236fac55'/>
<id>urn:sha1:2ffa7a35466212f31a0ffda5d948c49a236fac55</id>
<content type='text'>
Add device tree binding Documentation details for Qualcomm SM4250 LPASS
LPI(Low power Island) pinctrl device.

Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-1-a0342e47e21b@linaro.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: xilinx: Add support for function with pins</title>
<updated>2024-06-17T08:47:06Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@linux.dev</email>
</author>
<published>2024-06-10T22:35:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=58ba921150e96c5be718b92fd76e71ad82503c93'/>
<id>urn:sha1:58ba921150e96c5be718b92fd76e71ad82503c93</id>
<content type='text'>
Support specifying the function per-pin. The driver doesn't care
whether you use pins or groups for this purpose.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20240610223550.2449230-2-sean.anderson@linux.dev
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Describe I3C, USB</title>
<updated>2024-06-17T07:33:51Z</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@codeconstruct.com.au</email>
</author>
<published>2024-05-31T03:02:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1d1f3b8490b57c388a65f6c81fd867b1ec7e836b'/>
<id>urn:sha1:1d1f3b8490b57c388a65f6c81fd867b1ec7e836b</id>
<content type='text'>
I3C1 and I3C2 become muxed functions in the mass production release of
the AST2600. Also document the USB2A device and USB2B HID mux options.

Squash warnings such as:

    arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dtb: pinctrl: usb2ad_default:function:0: 'USB2AD' is not one of ['ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'EMMC', 'ESPI', 'ESPIALT', 'FSI1', 'FSI2', 'FWQSPI', 'FWSPIABR', 'FWSPID', 'FWSPIWP', 'GPIT0', 'GPIT1', 'GPIT2', 'GPIT3', 'GPIT4', 'GPIT5', 'GPIT6', 'GPIT7', 'GPIU0', 'GPIU1', 'GPIU2', 'GPIU3', 'GPIU4', 'GPIU5', 'GPIU6', 'GPIU7', 'I2C1', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C15', 'I2C16', 'I2C2', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'I3C3', 'I3C4', 'I3C5', 'I3C6', 'JTAGM', 'LHPD', 'LHSIRQ', 'LPC', 'LPCHC', 'LPCPD', 'LPCPME', 'LPCSMI', 'LSIRQ', 'MACLINK1', 'MACLINK2', 'MACLINK3', 'MACLINK4', 'MDIO1', 'MDIO2', 'MDIO3', 'MDIO4', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NR
 I4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PWM0', 'PWM1', 'PWM10', 'PWM11', 'PWM12', 'PWM13', 'PWM14', 'PWM15', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'PWM8', 'PWM9', 'RGMII1', 'RGMII2', 'RGMII3', 'RGMII4', 'RMII1', 'RMII2', 'RMII3', 'RMII4', 'RXD1', 'RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT15', 'SALT16', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SD1', 'SD2', 'SGPM1', 'SGPM2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1ABR', 'SPI1CS1', 'SPI1WP', 'SPI2', 'SPI2CS1', 'SPI2CS2', 'TACH0', 'TACH1', 'TACH10', 'TACH11', 'TACH12', 'TACH13', 'TACH14', 'TACH15', 'TACH2', 'TACH3', 'TACH4', 'TACH5', 'TACH6', 'TACH7', 'TACH8', 'TACH9', 'THRU0', 'THRU1', 'THRU2', 'THRU3', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART10', 'UART11', 'UART12', 'UART13', 'UART6', 'UART7', 'UART8', 'UART9', 'USBAD', 'USBADP', 'USB2AH', 'USB2AHP', 'USB
 2BD', 'USB2BH', 'VB', 'VGAHS', 'VGAVS', 'WDTRST1', 'WDTRST2', 'WDTRST3', 'WDTRST4']

Signed-off-by: Andrew Jeffery &lt;andrew@codeconstruct.com.au&gt;
Acked-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-3-a6fe2281a1b8@codeconstruct.com.au
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: aspeed,ast2500-pinctrl: Describe SGPM</title>
<updated>2024-06-17T07:33:51Z</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@codeconstruct.com.au</email>
</author>
<published>2024-05-31T03:02:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=757d04a4730004eec3b3d6346372ececd67f9b6b'/>
<id>urn:sha1:757d04a4730004eec3b3d6346372ececd67f9b6b</id>
<content type='text'>
Squash warnings such as:

    arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dtb: pinctrl@80: sgpm_default:groups:0: 'SGPM' is not one of ['ACPI', 'ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'DDCCLK', 'DDCDAT', 'ESPI', 'FWSPICS1', 'FWSPICS2', 'GPID0', 'GPID2', 'GPID4', 'GPID6', 'GPIE0', 'GPIE2', 'GPIE4', 'GPIE6', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'LAD0', 'LAD1', 'LAD2', 'LAD3', 'LCLK', 'LFRAME', 'LPCHC', 'LPCPD', 'LPCPLUS', 'LPCPME', 'LPCRST', 'LPCSMI', 'LSIRQ', 'MAC1LINK', 'MAC2LINK', 'MDIO1', 'MDIO2', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NRI4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PNOR', 'PWM0', 'PWM1', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'RGMII1', 'RGMII2', 'RMII1', 'RMII2', 'RXD1', '
 RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SCL1', 'SCL2', 'SD1', 'SD2', 'SDA1', 'SDA2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1CS1', 'SPI1DEBUG', 'SPI1PASSTHRU', 'SPI2CK', 'SPI2CS0', 'SPI2CS1', 'SPI2MISO', 'SPI2MOSI', 'TIMER3', 'TIMER4', 'TIMER5', 'TIMER6', 'TIMER7', 'TIMER8', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART6', 'USB11BHID', 'USB2AD', 'USB2AH', 'USB2BD', 'USB2BH', 'USBCKI', 'VGABIOSROM', 'VGAHS', 'VGAVS', 'VPI24', 'VPO', 'WDTRST1', 'WDTRST2']

Signed-off-by: Andrew Jeffery &lt;andrew@codeconstruct.com.au&gt;
Acked-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-2-a6fe2281a1b8@codeconstruct.com.au
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
