<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/Documentation/devicetree/bindings/soc/mediatek, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/soc/mediatek?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/Documentation/devicetree/bindings/soc/mediatek?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-02-17T10:07:23Z</updated>
<entry>
<title>dt-bindings: pwrap: mediatek: add pwrap support for MT6779</title>
<updated>2020-02-17T10:07:23Z</updated>
<author>
<name>Argus Lin</name>
<email>argus.lin@mediatek.com</email>
</author>
<published>2020-02-16T06:17:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=305ce1dce9d8046d44a322cb3ef5a6574cf86721'/>
<id>urn:sha1:305ce1dce9d8046d44a322cb3ef5a6574cf86721</id>
<content type='text'>
Add binding document of pwrap for MT6779 SoCs.

Signed-off-by: Argus Lin &lt;argus.lin@mediatek.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: mediatek: add MT6765 power dt-bindings</title>
<updated>2020-01-10T10:00:36Z</updated>
<author>
<name>Mars Cheng</name>
<email>mars.cheng@mediatek.com</email>
</author>
<published>2019-07-12T09:43:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=56f6737167ca733a6334d8313030f5a22761a439'/>
<id>urn:sha1:56f6737167ca733a6334d8313030f5a22761a439</id>
<content type='text'>
This adds power dt-bindings for MT6765

Signed-off-by: Mars Cheng &lt;mars.cheng@mediatek.com&gt;
Signed-off-by: Owen Chen &lt;owen.chen@mediatek.com&gt;
Signed-off-by: Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: power: Convert Generic Power Domain bindings to json-schema</title>
<updated>2019-11-14T16:46:16Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2019-10-30T17:32:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5279a3d8bedea477eaaaddedc3dd5fa62b86cfd7'/>
<id>urn:sha1:5279a3d8bedea477eaaaddedc3dd5fa62b86cfd7</id>
<content type='text'>
Convert Generic Power Domain bindings to DT schema format using
json-schema.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2019-05-16T16:19:14Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-05-16T16:19:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=dc413a90edbe715bebebe859dc072ef73d490d70'/>
<id>urn:sha1:dc413a90edbe715bebebe859dc072ef73d490d70</id>
<content type='text'>
Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms and a couple of the small driver
  subsystems we merge through our tree:

  Among the larger pieces:

   - Power management improvements for TI am335x and am437x (RTC
     suspend/wake)

   - Misc new additions for Amlogic (socinfo updates)

   - ZynqMP FPGA manager

   - Nvidia improvements for reset/powergate handling

   - PMIC wrapper for Mediatek MT8516

   - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
  soc: aspeed: fix Kconfig
  soc: add aspeed folder and misc drivers
  spi: zynqmp: Fix build break
  soc: imx: Add generic i.MX8 SoC driver
  MAINTAINERS: Update email for Qualcomm SoC maintainer
  memory: tegra: Fix a typos for "fdcdwr2" mc client
  Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
  memory: tegra: Replace readl-writel with mc_readl-mc_writel
  memory: tegra: Fix integer overflow on tick value calculation
  memory: tegra: Fix missed registers values latching
  ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
  optee: allow to work without static shared memory
  soc/tegra: pmc: Move powergate initialisation to probe
  soc/tegra: pmc: Remove reset sysfs entries on error
  soc/tegra: pmc: Fix reset sources and levels
  soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A
  soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  firmware: xilinx: Add fpga API's
  ...
</content>
</entry>
<entry>
<title>dt-bindings: soc: fix a typo for MT7623A</title>
<updated>2019-04-15T17:29:29Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-02-17T13:50:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9ccd75c55ac50f0ac23cc5bbb724613d2d7f1c89'/>
<id>urn:sha1:9ccd75c55ac50f0ac23cc5bbb724613d2d7f1c89</id>
<content type='text'>
This fixes a typo for MT7623A

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: mediatek: update bindings for MT7629 SoC</title>
<updated>2019-04-15T17:29:28Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-02-17T13:50:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c4fcbf1186e777c315d934202e9f0faf1987fe3a'/>
<id>urn:sha1:c4fcbf1186e777c315d934202e9f0faf1987fe3a</id>
<content type='text'>
This updates bindings for MT7629 SoC, which includes very basic items
such as system timer, UART, sysirq and scpsys unit.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pwrap: mediatek: add pwrap support for MT8516</title>
<updated>2019-04-12T17:42:24Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2019-03-23T21:15:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4bad8b0709f59cc210207201b2cba86e4fc28bf5'/>
<id>urn:sha1:4bad8b0709f59cc210207201b2cba86e4fc28bf5</id>
<content type='text'>
Add binding documentation of pwrap for MT8516 SoCs.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pwrap: mediatek: add pwrap support for MT6765</title>
<updated>2018-09-25T15:26:05Z</updated>
<author>
<name>Argus Lin</name>
<email>argus.lin@mediatek.com</email>
</author>
<published>2018-09-04T12:31:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0db3bd82546039f4bf434d378bafe4416b82b757'/>
<id>urn:sha1:0db3bd82546039f4bf434d378bafe4416b82b757</id>
<content type='text'>
Add binding document of pwrap for MT6765 SoCs.

Signed-off-by: Argus Lin &lt;argus.lin@mediatek.com&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: mediatek: add compatible for mt8183 pwrap</title>
<updated>2018-09-25T13:27:20Z</updated>
<author>
<name>Hsin-Hsiung Wang</name>
<email>hsin-hsiung.wang@mediatek.com</email>
</author>
<published>2018-09-19T07:25:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6d0ca9dbb6d199cb2adeb40da3fea3c4ece6f092'/>
<id>urn:sha1:6d0ca9dbb6d199cb2adeb40da3fea3c4ece6f092</id>
<content type='text'>
This adds dt-binding documentation of pwrap for Mediatek MT8183 SoC
Platform.

Signed-off-by: Hsin-Hsiung Wang &lt;hsin-hsiung.wang@mediatek.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pwrap: mediatek: add pwrap support for MT6797</title>
<updated>2018-07-16T13:50:17Z</updated>
<author>
<name>Argus Lin</name>
<email>argus.lin@mediatek.com</email>
</author>
<published>2018-06-11T10:49:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7de7f9520e55ec4afa45928bc7c7c57c5aab4875'/>
<id>urn:sha1:7de7f9520e55ec4afa45928bc7c7c57c5aab4875</id>
<content type='text'>
Add binding document of pwrap for MT6797 SoCs.

Signed-off-by: Argus Lin &lt;argus.lin@mediatek.com&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
</feed>
