<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/arc/include/asm/entry-arcv2.h, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/arc/include/asm/entry-arcv2.h?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/arc/include/asm/entry-arcv2.h?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-03-16T17:30:49Z</updated>
<entry>
<title>ARC: add support for DSP-enabled userspace applications</title>
<updated>2020-03-16T17:30:49Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2020-03-05T20:02:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7321e2ea0d6aece516a9c0827028ecda2ccaeae9'/>
<id>urn:sha1:7321e2ea0d6aece516a9c0827028ecda2ccaeae9</id>
<content type='text'>
To be able to run DSP-enabled userspace applications we need to
save and restore following DSP-related registers:
At IRQ/exception entry/exit:
 * DSP_CTRL (save it and reset to value suitable for kernel)
 * ACC0_LO, ACC0_HI (we already save them as r58, r59 pair)
At context switch:
 * ACC0_GLO, ACC0_GHI
 * DSP_BFLY0, DSP_FFT_CTRL

Reviewed-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARC: handle DSP presence in HW</title>
<updated>2020-03-16T17:23:44Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2020-03-05T20:02:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4827d0cf744e7e9cc73f10e1f4eaca904a3868c1'/>
<id>urn:sha1:4827d0cf744e7e9cc73f10e1f4eaca904a3868c1</id>
<content type='text'>
When DSP extensions are present, some of the regular integer instructions
such as DIV, MACD etc are executed in the DSP unit with semantics alterable
by flags in DSP_CTRL aux register. This register is writable by userspace
and thus can potentially affect corresponding instructions in kernel code,
intentionally or otherwise. So safegaurd kernel by effectively disabling
DSP_CTRL upon bootup and every entry to kernel.

Do note that for this config we simply zero out the DSP_CTRL reg assuming
userspace doesn't really care about DSP. The next patch caters to the DSP
aware userspace where this reg is saved/restored upon kernel entry/exit.

Reviewed-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARC: pt_regs: remove hardcoded registers offset</title>
<updated>2019-12-28T21:05:08Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2019-12-27T18:03:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7ecc6c1d5c8dbc713c647512a5267ca0eafe3e1c'/>
<id>urn:sha1:7ecc6c1d5c8dbc713c647512a5267ca0eafe3e1c</id>
<content type='text'>
Replace hardcoded registers offset numbers by calculated via
offsetof.

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: entry: early return from exception need not clear U &amp; DE bits</title>
<updated>2019-08-05T07:01:29Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>Alexey.Brodkin@synopsys.com</email>
</author>
<published>2019-07-16T20:50:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=97abfd5d801abb6eac35e2d7d725123950e2153d'/>
<id>urn:sha1:97abfd5d801abb6eac35e2d7d725123950e2153d</id>
<content type='text'>
Exception handlers call FAKE_RET_FROM_EXCPN to
 - clear AE bit: drop down from exception active to pure kernel mode
   allowing further excptions
 - set IE bit: re-enable interrupts

It additionally also clears U bit (user mode) and DE bit (delay slot
execution) which is redundant as hardware does that already on any taken
exception. Morevoer the current software clearing is bogus anyways as
the KFLAG instruction being used for purpose can't possibly write those
bits anyways.

So don't pretend to clear them.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
[vgupta: rewrote changelog]
</content>
</entry>
<entry>
<title>ARC: entry: EV_Trap expects r10 (vs. r9) to have exception cause</title>
<updated>2019-07-08T08:24:44Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2019-05-15T23:08:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=68e5c6f073bcf70da5f8eef88eb2d98f7c560bb6'/>
<id>urn:sha1:68e5c6f073bcf70da5f8eef88eb2d98f7c560bb6</id>
<content type='text'>
avoids 1 MOV instruction in light of double load/store code

Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: entry: rewrite to enable use of double load/stores LDD/STD</title>
<updated>2019-07-01T18:02:22Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2019-05-15T22:36:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a4880801a72ecc2dcdfa432f81a754f3e7438567'/>
<id>urn:sha1:a4880801a72ecc2dcdfa432f81a754f3e7438567</id>
<content type='text'>
 - the motivation was to be remove blatent copy-paste due to hasty support
   of CONFIG_ARC_IRQ_NO_AUTOSAVE support

 - but with refactoring we could use LDD/STD to greatly optimize the code

Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: entry: avoid a branch</title>
<updated>2019-07-01T18:02:22Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2019-05-10T23:24:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ab854bfcd310b5872fe12eb8d3f2c30fe427f8f7'/>
<id>urn:sha1:ab854bfcd310b5872fe12eb8d3f2c30fe427f8f7</id>
<content type='text'>
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: entry: push out the Z flag unclobber from common EXCEPTION_PROLOGUE</title>
<updated>2019-07-01T18:02:22Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2019-04-10T02:16:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=23c0cbd0c75c3b564850294427fd2be2bc2a015b'/>
<id>urn:sha1:23c0cbd0c75c3b564850294427fd2be2bc2a015b</id>
<content type='text'>
Upon a taken interrupt/exception from User mode, HS hardware auto sets Z flag.
This helps shave a few instructions from EXCEPTION_PROLOGUE by eliding
re-reading ERSTATUS and some bit fiddling.

However TLB Miss Exception handler can clobber the CPU flags and still end
up in EXCEPTION_PROLOGUE in the slow path handling TLB handling case:

   EV_TLBMissD
     do_slow_path_pf
       EV_TLBProtV (aliased to call_do_page_fault)
          EXCEPTION_PROLOGUE

As a result, EXCEPTION_PROLOGUE need to "unclobber" the Z flag which this
patch changes. It is now pushed out to TLB Miss Exception handler.
The reasons beings:

 - The flag restoration is only needed for slowpath TLB Miss Exception
   handling, but currently being in EXCEPTION_PROLOGUE penalizes all
   exceptions such as ProtV and syscall Trap, where Z flag is already
   as expected.

 - Pushing unclobber out to where it was clobbered is much cleaner and
   also serves to document the fact.

 - Makes EXCEPTION_PROLGUE similar to INTERRUPT_PROLOGUE so easier to
   refactor the common parts which is what this series aims to do

Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: entry: comments about hardware auto-save on taken interrupts</title>
<updated>2019-07-01T18:02:22Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2019-04-09T23:55:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=45869eb0c0afd72bd5ab2437d4b00915697c044a'/>
<id>urn:sha1:45869eb0c0afd72bd5ab2437d4b00915697c044a</id>
<content type='text'>
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>ARCv2: support manual regfile save on interrupts</title>
<updated>2019-02-21T19:03:18Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2018-06-06T17:20:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e494239a007e601448110ac304fe055951f9de3b'/>
<id>urn:sha1:e494239a007e601448110ac304fe055951f9de3b</id>
<content type='text'>
There's a hardware bug which affects the HSDK platform, triggered by
micro-ops for auto-saving regfile on taken interrupt. The workaround is
to inhibit autosave.

Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
</feed>
