wireguard-linux/arch/arc/include/asm/mmu.h, branch jd/unified-crypt-queue

ARC: mm: tlb flush optim: Make TLBWriteNI fallback to TLBWrite if not available

2019-10-28T19:12:32Z

TLBWriteNI was introduced in MMUv2 (to not invalidate uTLBs in Fast Path TLB Refill Handler). To avoid #ifdef'ery make it fallback to TLBWrite availabel on all MMUs. This will also help with next change Signed-off-by: Vineet Gupta

ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg

2019-10-28T19:12:31Z

ARC700 exception (and intr handling) didn't have auto stack switching thus had to rely on stashing a reg temporarily (to free it up) at a known place in memory, allowing to code up the low level stack switching. This however was not re-entrant in SMP which thus had to repurpose the per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg pointer (vs. reading it from mm struct) The newer HS cores do have auto-stack switching and thus even SMP builds can use the MMU SCRATCH reg as originally intended. This patch fixes the restriction to ARC700 SMP builds only Signed-off-by: Vineet Gupta

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC

2017-08-04T08:26:35Z

PAE40 confiuration in hardware extends some of the address registers for TLB/cache ops to 2 words. So far kernel was NOT setting the higher word if feature was not enabled in software which is wrong. Those need to be set to 0 in such case. Normally this would be done in the cache flush / tlb ops, however since these registers only exist conditionally, this would have to be conditional to a flag being set on boot which is expensive/ugly - specially for the more common case of PAE exists but not in use. Optimize that by zero'ing them once at boot - nobody will write to them afterwards Cc: stable@vger.kernel.org #4.4+ Signed-off-by: Vineet Gupta

ARC: mm: fix build failure in linux-next for UP builds

2017-05-05T19:06:33Z

kisskb build service reported ARC defconfig build failures in linux-next | arch/arc/include/asm/mmu.h:75:21: error: 'NR_CPUS' undeclared here (not in a function) | make[3]: *** [arch/arc/mm/ioremap.o] Error 1 | make[2]: *** [arch/arc/mm] Error 2 | make[1]: *** [arch/arc] Error 2 which I bisected to a subtle side-effect of a totally benign mm patch ("mm, vmalloc: properly track vmalloc users") which caused a header include chain deviation - asm/mmu.h using NR_CPUS before including linux/threads.h Fix that by adding the dependnet header and while it at fix a related header to include linux headers aheads of asm headers as sometimes that slso triggers such issues ! Reported-by: noreply@ellerman.id.au Signed-off-by: Vineet Gupta

ARC: mm: PAE40 support

2015-10-29T13:11:30Z

This is the first working implementation of 40-bit physical address extension on ARCv2. Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta

ARCv2: MMUv4: TLB programming Model changes

2015-06-22T08:36:55Z

Signed-off-by: Vineet Gupta

ARC: [SMP] ASID allocation

2013-11-06T05:11:45Z

-Track a Per CPU ASID counter -mm-per-cpu ASID (multiple threads, or mm migrated around) Signed-off-by: Vineet Gupta

ARC: fix new Section mismatches in build (post __cpuinit cleanup)

2013-09-05T13:49:06Z

--------------->8-------------------- WARNING: vmlinux.o(.text+0x708): Section mismatch in reference from the function read_arc_build_cfg_regs() to the function .init.text:read_decode_cache_bcr() WARNING: vmlinux.o(.text+0x702): Section mismatch in reference from the function read_arc_build_cfg_regs() to the function .init.text:read_decode_mmu_bcr() --------------->8-------------------- Signed-off-by: Vineet Gupta

ARC: [ASID] Track ASID allocation cycles/generations

2013-08-30T16:12:19Z

This helps remove asid-to-mm reverse map While mm->context.id contains the ASID assigned to a process, our ASID allocator also used asid_mm_map[] reverse map. In a new allocation cycle (mm->ASID >= @asid_cache), the Round Robin ASID allocator used this to check if new @asid_cache belonged to some mm2 (from prev cycle). If so, it could locate that mm using the ASID reverse map, and mark that mm as unallocated ASID, to force it to refresh at the time of switch_mm() However, for SMP, the reverse map has to be maintained per CPU, so becomes 2 dimensional, hence got rid of it. With reverse map gone, it is NOT possible to reach out to current assignee. So we track the ASID allocation generation/cycle and on every switch_mm(), check if the current generation of CPU ASID is same as mm's ASID; If not it is refreshed. (Based loosely on arch/sh implementation) Signed-off-by: Vineet Gupta