wireguard-linux/arch/arm/boot/compressed/head.S, branch jd/unified-crypt-queue

efi/arm: Deal with ADR going out of range in efi_enter_kernel()

2020-04-14T06:32:14Z

Commit 0698fac4ac2a ("efi/arm: Clean EFI stub exit code from cache instead of avoiding it") introduced a PC-relative reference to 'call_cache_fn' into efi_enter_kernel(), which lives way at the end of head.S. In some cases, the ARM version of the ADR instruction does not have sufficient range, resulting in a build error: arch/arm/boot/compressed/head.S:1453: Error: invalid constant (fffffffffffffbe4) after fixup ARM defines an alternative with a wider range, called ADRL, but this does not exist for Thumb-2. At the same time, the ADR instruction in Thumb-2 has a wider range, and so it does not suffer from the same issue. So let's switch to ADRL for ARM builds, and keep the ADR for Thumb-2 builds. Reported-by: Arnd Bergmann Tested-by: Arnd Bergmann Signed-off-by: Ard Biesheuvel Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200409130434.6736-6-ardb@kernel.org

Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

2020-04-03T18:20:16Z

Pull ARM updates from Russell King: - replace setup_irq() with request_irq() for ebsa110, footbridge, rpc - fix clang assembly error in kexec code - remove .fixup section in boot stub - decompressor / EFI cache flushing updates * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8966/1: rpc: replace setup_irq() by request_irq() ARM: 8965/2: footbridge: replace setup_irq() by request_irq() ARM: 8964/1: ebsa110: replace setup_irq() by request_irq() ARM: 8962/1: kexec: drop invalid assembly argument ARM: decompressor: switch to by-VA cache maintenance for v7 cores ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance ARM: decompressor: factor out routine to obtain the inflated image size ARM: 8959/1: Remove unused .fixup section in boot stub ARM: allow unwinder to unwind recursive functions

efi/arm: Clean EFI stub exit code from cache instead of avoiding it

2020-02-29T09:16:57Z

The following commit: c7225494b ("efi/arm: Work around missing cache maintenance in decompressor handover") modified the EFI handover code written in assembler to work around the missing cache maintenance of the piece of code that is executed after the MMU and caches are turned off. Due to the fact that this sequence incorporates a subroutine call, cleaning that code from the cache is not a matter of simply passing the start and end of the currently running subroutine into cache_clean_flush(), which is why instead, the code jumps across into the cleaned copy of the image. However, this assumes that this copy is executable, and this means we expect EFI_LOADER_DATA regions to be executable as well, which is not a reasonable assumption to make, even if this is true for most UEFI implementations today. So change this back, and add a cache_clean_flush() call to cover the remaining code in the subroutine, and any code it may execute in the context of cache_off(). Signed-off-by: Ard Biesheuvel Signed-off-by: Ingo Molnar Cc: linux-efi@vger.kernel.org Cc: Ingo Molnar Cc: Thomas Gleixner Cc: David Hildenbrand Cc: Heinrich Schuchardt Cc: Tom Lendacky Link: https://lore.kernel.org/r/20200228121408.9075-5-ardb@kernel.org

ARM: decompressor: switch to by-VA cache maintenance for v7 cores

2020-02-27T10:15:50Z

Update the v7 cache_clean_flush routine to take into account the memory range passed in r0/r1, and perform cache maintenance by virtual address on this range instead of set/way maintenance, which is inappropriate for the purpose of maintaining the cached state of memory contents. Since this removes any use of the stack in the implementation of cache_clean_flush(), we can also drop some code that manages the value of the stack pointer before calling it. Tested-by: Tony Lindgren Tested-by: Linus Walleij Signed-off-by: Ard Biesheuvel

ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance

2020-02-27T10:15:35Z

In preparation for turning the decompressor's cache clean/flush operations into proper by-VA maintenance for v7 cores, pass the start and end addresses of the regions that need cache maintenance into cache_clean_flush in registers r0 and r1. Currently, all implementations of cache_clean_flush ignore these values, so no functional change is expected as a result of this patch. Tested-by: Tony Lindgren Tested-by: Linus Walleij Signed-off-by: Ard Biesheuvel

ARM: decompressor: factor out routine to obtain the inflated image size

2020-02-27T10:15:10Z

Before adding another reference to the inflated image size, factor out the slightly complicated way of loading the unaligned little-endian constant from the end of the compressed data. Tested-by: Tony Lindgren Tested-by: Linus Walleij Signed-off-by: Ard Biesheuvel

efi/libstub/arm: Make efi_entry() an ordinary PE/COFF entrypoint

2020-02-22T22:37:37Z

Expose efi_entry() as the PE/COFF entrypoint directly, instead of jumping into a wrapper that fiddles with stack buffers and other stuff that the compiler is much better at. The only reason this code exists is to obtain a pointer to the base of the image, but we can get the same value from the loaded_image protocol, which we already need for other reasons anyway. Update the return type as well, to make it consistent with what is required for a PE/COFF executable entrypoint. Signed-off-by: Ard Biesheuvel

efi/arm: Pass start and end addresses to cache_clean_flush()

2020-02-22T18:04:57Z

efi/arm: Work around missing cache maintenance in decompressor handover

2020-02-22T18:04:54Z

The EFI stub executes within the context of the zImage as it was loaded by the firmware, which means it is treated as an ordinary PE/COFF executable, which is loaded into memory, and cleaned to the PoU to ensure that it can be executed safely while the MMU and caches are on. When the EFI stub hands over to the decompressor, we clean the caches by set/way and disable the MMU and D-cache, to comply with the Linux boot protocol for ARM. However, cache maintenance by set/way is not sufficient to ensure that subsequent instruction fetches and data accesses done with the MMU off see the correct data. This means that proceeding as we do currently is not safe, especially since we also perform data accesses with the MMU off, from a literal pool as well as the stack. So let's kick this can down the road a bit, and jump into the relocated zImage before disabling the caches. This removes the requirement to perform any by-VA cache maintenance on the original PE/COFF executable, but it does require that the relocated zImage is cleaned to the PoC, which is currently not the case. This will be addressed in a subsequent patch. Signed-off-by: Ard Biesheuvel

ARM: 8942/1: Revert "8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

2020-01-25T18:17:57Z

This reverts commit e17b1af96b2afc38e684aa2f1033387e2ed10029, which is no longer necessary now that the v7 specific routines take care not to issue CP15 barrier instructions before they are enabled in SCTLR. Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King